Paolo Bernardi

Politecnico di Torino | polito · DAUIN - Department of Control and Computer Engineering

This paper describes a hardware/software strategy for the effective and efficient management of several distributed Memory Built-In Self-Test (MBIST) units orchestrated by a single CPU to enable the parallel testing of several memory banks. Experimental testing of the implementation on an Infineon chip shows up to a 25% test time reduction compared...

Complexity and performance of Automotive System-on-Chips have exponentially grown in the last decade, also according to technology advancements. Unfortunately, this trend directly and profoundly impacts modern Electronic Design Automation tools, which must handle very large amounts of logic gates. The consequence is an exponential increase in compu...

With the explosion in the size of off-the-shelf integrated circuits and the advent of novel techniques related to failure modes, commercial Automatic Test Pattern Generator and fault simulation engines are often insufficient to measure the coverage of particular metrics. Consequently, a general working framework consists of storing simulation trace...

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (M...

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We disc...

With the introduction of the ISO26262 standard in the automotive field, numerous solutions for the in-field and on-line testing have been proposed. Among the several test solutions available, the Built-In Self-Test (BIST) approach is the most used for manufacturing test of chips, while the Software-Based Self-Test (SBST) approach is the most common...

Safety-critical electronics components require thermal and electrical stress phases at the end of manufacturing test to screen weak devices. It is possible to optimize the stress induced during the screening phase of Burn-In by running in parallel different types of stress procedures. In previous works, stress procedures of CPU, RAM memory and FLAS...

The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoC). This paper highlights problematic aspects of a Burn-In flow and describes a two-layered adaptive technique that permits to optimize the stress application and strongly reduce BI test time. At the SoC level, the described methodology adaptively copes with FLA...

The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoCs). This paper proposes an optimized Test-During-Burn-In (TDBI) flow that takes advantage of the parallel execution of several types of stress procedures in which many components are carefully interleaved. The proposed methodology permits to significantly reduc...

Nowadays, Self-Test strategies for testing embedded processors are increasingly diffused, especially for safety critical systems. Test programs can be effectively used for this purpose. This paper describes a set of systematic self-test techniques for in-order dual-issue embedded processors. The paper shows how to produce test programs suitable for...

At the end of the manufacturing cycle of digital circuits, a stress phase is mandatory in order to remove from the final device population the weak devices that may result in early life failures. Devices used in safety critical environments must undergo this phase that is usually accomplished by exploiting the Burn-In (BI) process. Unfortunately, B...

Embedded SRAM elements are becoming the main detractor of the overall System-on-Chip (SoC) yield. To increase the reliability of embedded SRAMs, the use of Error Correction Code (ECC) has been widely adopted. Depending on the implemented ECC scheme, SRAMs can detect/correct the presence of one or more transient errors during the mission time. In th...

Structural test is widely adopted to ensure high quality for a given product. The availability of many commercial tools and the use of fault models make it very easy to generate and to evaluate. Despite its efficiency, structural test is also known for the risk of over-testing that may lead to yield loss. This problem is mainly due to the fact that...

Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DM...

This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible intra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vec...

Burn-In (BI) test is usually applied in manufacturing process to screen out chip early life failures, especially for safety critical applications. Unfortunately, this test method has elevated costs for companies.

Self-Test strategies for testing embedded processors are increasingly diffused. In this paper, we describe a set of self-test techniques tackling dual issue embedded processors. The paper details how to produce test programs suitable to detect stuck-at faults in computational modules belonging to dual issue processors. The proposed technique is aim...

This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of Transition Delay (TD) Faults, and exploiting this relationship to produce effective patterns. The approach encompasses several steps: once a Gate Delay Fau...

With continuous technology scaling, both quality and reliability are becoming major concerns for ICs due to extreme variations, non-ideal voltage scaling, etc. (not to mention the business pressure leading to shorter-time to market). One-time-factory manufacturing test is not sufficient anymore, and in-field testing (e.g., periodically, at power-on...

With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. Several works analyze the impact of intra-cell defects w.r.t. the test quality. However, to the best of our knowledge, none of them target intra-cell defects affecting scan flip-flops. This paper presents an evaluation of the effect...

Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when gene...

The paper is dealing with the in-field test of the decode unit of RIS C processors through functional test programs following the SBST approach. The paper details a strategy based on instruction classification and manipulation, and signatures collection. The method does not require the knowledge of detailed implementation information (e.g., the net...

Testing processor cores embedded in systems-on-chip (SoCs) is a major concern for industry nowadays. In this paper, we describe a novel solution which merges the SBST and BIST principles. The technique we propose forces the processor to execute a compact SBST-like test sequence by using a hardware module called MIcroprocessor Hardware Self-Test (MI...

When the result of a previous instruction is needed in the pipeline before it is available, a 'data hazard' occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the micropr...

A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly state the fault coverage figures to be achieved with respect to permanent faults. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Desig...

This paper presents an evaluation framework for functional programs. Programs are evaluated w.r.t. functional and structural metrics. The goal is to verify if the targeted functional programs can be re-used for verification and test purposes.

With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.

Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faul...

When the result of a previous instruction is needed in the pipeline before it is available, a “data hazard” occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the micropr...

System on Chip devices include an increasing number of embedded memory cores, whose test during the operational phase is often a strict requirement, especially for safety-critical applications. This paper proposes a new memory test method combining the characteristics of hardware and software solutions: the test is performed by the microcontroller/...

This letter studies the RF property of a p-core voltage-controlled oscillator (VCO) stressed at elevated supply voltage. The dual-resonance p-core LC-tank VCO has been fabricated using 0.18 μm CMOS technology, and the dual-resonance LC resonator is consisted of a parallel-tuned LC resonator and a series resonant resonator. The RF circuit parameters...

A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly describe fault coverage figures to be achieved. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Design for Testability) is often the on...

Nowadays, Software-Based Self-Test (SBST) is growing in importance especially in the on-line test scenario for safety critical systems such as automotive. This paper concentrates on the coverage by SBST of those faults in the scan chain that can impact the behavior of the embedded processor while working in its application field. A technique is des...

Functional testing of embedded processors is a challenging task and additional constraints are imposed when a functional test procedure has to be executed online. In the latter case, a significant amount of the processor faults cannot be detected since related to the debug/test circuitry or because of memory configuration constraints. In this paper...

High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during functional mode, being as high as possible but not crossing the frontier of over-consumption. Measuring power consumption is a v...

Software-based Self-Test (SBST) can be used during the mission phase of microprocessor-based systems to periodically assess the hardware integrity. However, several constraints are imposed to this approach, due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST programs to test...

A Branch Target Buffer (BTB) is a mechanism to support speculative execution in order to overcome the performance penalty caused by branch instructions in pipelined microprocessors. Being an intrinsically fault tolerant unit, it is hard to achieve a good fault coverage resorting to plain functional testing methods. In this paper we analyze the caus...

This paper describes the working principle and an implementation of a low-cost tester architecture supporting volume test and diagnosis of built-in self-test (BIST)-assisted embedded memory cores. The described tester architecture autonomously executes a diagnosis-oriented test program, adapting the stimuli at run-time, based on the collected test...

This paper deals with the on-line test of SoCs including cores equipped with BIST circuitry and IEEE 1500 wrappers. A method is proposed, which exploits an Infrastructure IP named OTC to manage the on-line test, the OTC module activates the test and provides the related results under the software control of the CPU, thus allowing the SoC to autonom...

This paper describes a novel modeling method for Gate Delay Faults. The methodology considers each Gate Delay Fault as equivalent to a set of Transition Delay Faults in the propagation paths of the affected port. The main advantage of using this model is that it does not need any explicit timing information and it allows to predict the effect of ga...

Testing embedded microprocessors at mission time is nowadays a requirement in many SoC applications. In this paper, we introduce a methodology where the detection of operational faults is performed while the normal operations are temporarily suspended, by means of an ad-hoc HW module connected to the address, data and control buses of the microproc...

This paper describes a tester architecture for Accelerometer and Gyroscope Micro-ElectroMechanical System (MEMS) devices test and calibration, allowing increased parallelism rate and process accuracy. The proposed tester architecture tackles some critical issues related to MEMS testing, such as mitigating mechanical concerns that potentially impact...

Today, electronic devices are increasingly employed in different fields, including safety- and mission-critical applications, where the quality of the product is an essential requirement. In the automotive field, on-line self-test is a dependability technique currently demanded by emerging industrial standards. This paper presents an approach emplo...

Reliability characterization is the industrial process intended to measure the useful life period and failure rate of a component population by exploiting stress mechanisms. The paper describes a methodology for the automatic generation of stress programs to be used during the reliability characterization process of Systems-on-Chip (SoC). The propo...

Today, electronic devices are increasingly employed in different fields, including safety- and mission-critical applications, where the quality of the product is an essential requirement. In the automotive field, the Software-Based Self-Test is a dependability technique currently demanded by industrial standards. This paper presents an approach emp...

In the recent years, the usage of embedded microprocessors in complex SoCs has become common practice. Their test is often a challenging task, due to their complexity, to the strict constraints coming from the environment and the application, and to the typical SoC design paradigm, where cores (including microprocessors) are often provided by third...

This poster outlines the working principle and an implementation of a tester architecture supporting MEMS calibration and testing; the tester works adaptively, providing electrical stimuli at run-time according to the collected results. The tester manages the calibration and testing process by means of a special hardware module, saving time and avo...

This paper proposes a programmable Built-In Self-Test (BIST) approach for DRAM test and diagnosis. The proposed architecture suits well for embedded core testing as well as for stacked and stand-alone DRAMs and it provides programmability features for executing both March and NPSF-oriented test algorithms. The proposed BIST structure is designed to...

Critical applications based on Systems-on-Chip (SoCs) require suitable techniques that are able to ensure a sufficient level of reliability. Several techniques have been proposed to improve fault detection and correction capabilities of faults affecting SoCs. This paper proposes a hybrid approach able to detect and correct the effects of transient...

Volume diagnosis is crucial for discovering the root causes of yield loss during the IC production flow. This process is time consuming and requires appropriate test equipment supporting diagnostic data storage. This paper proposes a novel methodology for significantly reducing the time and the data storage requirements for digital circuit diagnosi...

Semiconductor manufacturers aim at delivering high-quality new devices within shorter times in order to gain market shares. First silicon debug and diagnosis are important issues to be tackled in order to minimise the time-to-market and avoid expensive re-spins, while volume testing is necessary for guaranteeing acceptable quality levels. In this s...

This paper presents an exact and efficient Critical Path Tracing algorithm targeting fault simulation of both Transition and Stuck-at faults. The complexity of the proposed algorithm is linear in the number of gates traced during the path tracing process. Experimental results show the efficiency of the proposed approach on a set of benchmark circui...

An effective silicon debug and diagnosis process has to be supported by on-chip hardware structures, stimulation equipments and software tools for analysis. In this paper, the characteristics of a software tool for memory failure analysis are presented; this tool takes into account the memory topology and the executed memory test, and returns both...

Nanometric circuits and systems are increasingly susceptible to delay defects. This paper describes a strategy for the diagnosis of transition-delay faults in full-scan systems-on-a-chip (SOCs). The proposed methodology takes advantage of a suitably generated software-based self-test test set and of the scan-chains included in the final SOC design....

In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor VTH degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure us...

This paper proposes an efficient low-cost strategy for collecting data during radiation experiments on Systems-on-Chips (SoCs), exploiting the available on-chip Design for Testability (DfT) structures devised for manufacturing test.The approach combines hardware test and diagnostic features with suitable software tools, which enable accurate measur...

This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally ef...

This paper discusses the fabrication challenges introduced by products targeted to the automotive market segment. Different methods to enhance intrinsic design robustness, along with the design flow will be discussed. Experimental results from simulations and daftafom the field will be presented to support the proposed solutions.

Radio frequency identification (RFID) is an identification technology that is particularly interesting for several kinds of physical objects, either living beings or inanimate items. In this paper we propose to use it to implement an anti-counterfeit mechanism in selected wine production environments. Using a personal digital assistant (PDA) with a...