Muhammad Yasir Qadri

University of Essex · School of Computer Science and Electronic Engineering

Emergence of modern multicore architectures has made runtime reconfiguration of system resources possible. All reconfigurable system resources constitute a design space and the proper selection of configuration of these resources to improve the system performance is known as Design Space Exploration (DSE). This reconfiguration feature helps in appr...

Modern multicore architectures have an ability to allocate optimum system resources for a specific application to have improved energy and throughput balance. The system resources can be optimized automatically by using optimization algorithms. State-of-the-art using optimization algorithm in the field of such architectures has shown promising resu...

Modern multicore architectures comprise a large set of components and parameters that require being matched to achieve the best balance between power consumption and throughput performance for a particular application domain.The exploration of design space for finding the best power–throughput trade-off is a combinatorial optimization problem with...

Modern multicore architectures comprise a large set of components and parameters that require being matched to achieve the best balance between power consumption and throughput performance for a particular application domain. The exploration of design space for finding the best power–throughput trade-off is a combinatorial optimization problem with...

General trends in computer architecture are shifting more towards parallelism. Multicore architectures have proven to be a major step in processor evolution. With the advancement in multicore architecture, researchers are focusing on finding different solutions to fully utilize the power of multiple cores. With an ever-increasing number of cores on...

This paper demonstrates that interval type-2 Fuzzy Logic Systems (FLS’s) are suited to Multiprocessor System-on-a-Chip (MPSoC) design modeling because of their ability to handle the uncertainty associated with input parameters. This makes for a scalable modeling process, whereas prior usage of type-1 FLS’s for modeling inhibited scalability. Specif...

Image fusion is the process of combining two or more related images to produce a single output image, containing more relevant information than any one of the input images. The image-fusion process depends upon: the application domain; the number of images undergoing fusion; and the type of imagery, such as whether it is multi-spectral or multi-mod...

Increasing demand for better throughput and performance has motivated designers to come up with more sophisticated processors with innovative designs. Such designs for multicore architectures offer large amount of parallelism which is often underutilized and thus becomes overhead and liability. Due to these advancements, there has been a exponentia...

Most of recent research in multicore processor architectures has been shifted towards reconfigurable architectures due to increasing complexity of computing systems. These systems provide better application-specific energy and throughput balance with their reconfigurable behavior. They perform automatic run time resource allocation for an applicati...

This paper concerns the design space exploration of Reconfigurable Multi Processor System on Chip (MPSoC) architectures. Reconfiguration allows users to allocate optimum system resources for a specific application in such a way as to improve the energy and throughput balance. To achieve the best balance between power consumption and throughput perf...

Driven by the advances in hardware and software technologies, the term Internet of things has emerged as a worldwide framework of ‘smart’ internet-based interconnected electronic devices through web having a significant impact in the betterment of our traditional living style. The use of these web connected embedded devices, as Information and comm...

Multicore architectures are mainstream due to ever increasing demand of throughput by modern applications. However, the suboptimal utilization of available resources in these architectures may imply an inevitable energy overhead. This energy overhead can only be avoided if the multicore systems support reconfiguration of available resources as per...

Being an era of fast internet-based application environment, large volumes of relational data are being outsourced for business purposes. Therefore, ownership and digital rights protection has become one of the greatest challenges and among the most critical issues. This paper presents a novel fingerprinting technique to protect ownership rights of...

An energy-efficient architecture should jointly optimize energy consumption and throughput, as captured by the Energy-Delay-Square Product (ED²P) metric. This paper introduces a prefetch data buffer micro-architecture, which achieves that goal with the aid of software-inserted control words to govern the prefetch process. The proposed architecture...

Recent developments in wireless networks, MicroElectroMechanical systems technology and integrated circuits have enabled miniaturisation of micro/nano-sensor nodes. These low-power and intelligent nodes are placed in or around the human body in a strategic manner for numerous new, practical and innovative applications. These applications provide im...

The trade-off between performance and power consumptionfor dynamic and complex applications is inevitable andis considered as a key design challenge for system architects. Performance statistics for hard real time systems must be readilyavailable for a feedback system, specifically for reconfigurablearchitectures. The feedback in terms of performan...

The invention relates to the method of prefetching data in micro-processor buffer under software controls.

Standard benchmark tools play an integral part in the design process for performance evaluation of a computer system. A previously proposed tool, JetBench, is an Open Source multiprocessor benchmark that can be used to analyze the performance of a specific target platform. JetBench uses reaction-propulsion engine parameters and thermodynamical equa...

In the field of embedded system there exists a trade off between power/performance optimization, hence many heuristics and techniques were presented at various development levels such as hardware software co-design, schedulers and optimal code compilation. This paper presents an enhanced version of LEON3 architecture which includes support for run-...

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization...

Multi-Processor System on Chip (MPSoC) architectures have become a mainstream technology for obtaining performance improvements in computing platforms. With the increase in the number of cores, the role of cache memory has become pivotal. An ideal memory configuration is always desired to be fast and large; but, in fact, striking to balance between...

The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mu...

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system compone...

The emergence of Multi Processor System on Chip (MPSoC) architectures with reconfigurable options is revolutionizing general purpose processing. Reconfigurable architectures give us the opportunity to allocate system resources with respect to specific application requirements. Reconfigurable architectures can provide high throughput and low energy...

In this paper a Fuzzy logic based Controller has been proposed to reconfigure multi-processor system on chip (MPSoC) architecture according to the workload requirements. Mamdani and Sugeno Inference Engines are compared and analyzed to enhance the smooth regulation of reconfiguration in design space. The proposed MPSoC platform consists of 16 cores...

Complex algorithms particularly for real-time computer vision applications require significant amount of simulation time when implemented using Hardware Description Languages (HDLs). This increase in simulation time is mainly due to the use of OEM supplied IP Cores. In this paper we propose a methodology involving: 1) design partitioning, and 2) us...

This paper proposes a method of buffering instructions by software-based prefetching. The method allows low-end processors to improve their instruction throughput with a minimum of additional logic and power consumption. Low-end embedded processors do not employ caches for mainly two reasons. The first reason is that the overhead of cache implement...

Emergence of Multi Processor System on Chip (MPSoC) architectures with reconfigurable options is revolutionizing the general purpose processing. Reconfigurable architectures give us opportunity to allocate system resources with respect to specific application requirement. Reconfigurable architectures can provide high throughput and low energy consu...

Multicore architectures were introduced to mitigate the issue of increase in power dissipation with clock frequency. Introduction of deeper pipelines, speculative threading etc. for single core systems were not able to bring much increase in performance as compared to their associated power overhead. However for multicore architectures performance...

Real-time mission planning for Unmanned Aerial Vehicles (UAVs) is an important application that requires implementation of computer vision algorithms such as Locally Normalized Cross Correlation (LNCC), with greater accuracy and throughput. Although the LNCC algorithm is the prime choice for image matching, its real time hardware implementation has...

Multicore architectures offer an amount of parallelism that is often underutilized, as a result these underutilized resources become a liability instead of advantage. Inefficient resource sharing on the chip can have a negative impact on the performance of an application and may result in greater energy consumption. A large body of research now foc...

Embedded systems architectures have traditionally often been investigated and designed in order to achieve a greater throughput combined with minimum energy consumption. With the advent of reconfigurable architectures it is now possible to support algorithms to find optimal solutions for an improved energy and throughput balance. As a result of ong...

Performance comparison among various architectures is generally attained by using standard benchmark tools. This paper presents JetBench, an Open Source OpenMP based multicore benchmark application that could be used to analyse real time performance of a specific target platform. The application is designed to be platform independent by avoiding ta...

Recent developments in reconfigurable multiprocessor system on chip (MPSoC) have offered system designers a great amount of flexibility to exploit task concurrency with higher throughput and less energy consumption. This paper presents a novel fuzzy logic reconfiguration engine (FLRE) for coarse grain MPSoC reconfiguration that facilitates to ident...

With the increase of processor-memory performance gap, it has become important to gauge the performance of cache architectures so as to evaluate their impact on energy requirement and throughput of the system. Multilevel caches are found to be increasingly prevalent in the high-end processors. Additionally, the recent drive towards multicore system...

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistor...

Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathe...

Embedded processors are often characterized by limited resources and are optimized for specific applications. A rising number of battery powered applications has driven a trend towards increased energy efficiency sometimes even traded with performance. Particularly, lower power and low specification embedded processors lack on-chip cache memories....