Design of a low-power high-speed comparator in 0.13μm CMOS

Abstract

Comparator plays an important role in overall performance of analog to digital converters (ADC) in all modern electronic devices used in handheld to industrial applications. High-speed devices with low voltage and low power are considered essential nowadays. This paper presents a CMOS based comparator design using 0.13 μm CMOS process in Mentor Graphics for ADC applications. The primary goal of this research work is to design high-speed and low power comparator using pre-amplifier latch circuit. The proposed design is powered by 1.2V supply and the output signal exhibits only 0.62ns delay which is very much competitive to the other researches. The comparator dissipates only 1.5nW power which is the lowest reported to date. The proposed design is highly compact occupying only 256 μm2 of silicon space. The proposed circuit will be highly useful for the electronic industries where low-power, high-performance, and compactness of devices are the crucial concerns.

Full text

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2016 International Conference on Advances in Electrical, Electronic and System Engineering, 14-16 Nov 2016, Putrajaya,
Malaysia
978-1-5090-2889-4/16/$31.00 ©2016 IEEE 289

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