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A new lossless method of Huffman coding for text data compression and decompression process with FPGA implementation
Abstract
Digital compression for reducing data size is important because of bandwidth restriction. Compression technique is also named source coding. It defines the process of compressed data using less number of bits than uncompressed form. Compression is the technique for decreasing the amount of information used to represent data without decreasing the quality of the text. It also decreases the number of bits needed to storage or transmission in different media. Compression is a method that makes keeping of data easier for a large size of information. In this study, proposed Huffman design includes encoder and decoder based on new binary tree for improving usage of memory for text compression. A saving percentage of approximately 47.95% was achieved through the suggested way. In this research, Huffman encoder and decoder were created using Verilog HDL. Huffman design was achieved by using a binary tree. ModelSim simulator tool from Mentor Graphics was used for functional verification and simulation of the design modules. FPGA was used for Huffman implementation.
... Reliability, design cycle time, testability, and design complexity are among the other characteristics that are impacted by low-power design systems. The two main trade-offs taken into account while building a VLSI system are chip area and speed [6], [7]. ...
In the field of information theory, the significance of low-power techniques cannot be overstated. Among these, clock gating stands out as a potent method to mitigate power dissipation in synchronous designs. The landscape has been further shaped by VLSI innovations, which, in their initial stages, necessitated substantial equipment, incurred high power consumption, and exhibited occasional unreliability. This paper explores the evolution from these challenges to a paradigm where advancements in VLSI technology have resulted in smaller, more affordable, reliable, and power-efficient systems. Focusing on the Arithmetic Logical Unit (ALU) design, our study presents a comparative analysis of power consumption across various existing clock gating techniques. Introducing an innovative signal clock gating method, we address contemporary challenges with an accessible mechanism, enhancing immunity. Our proposed Gated Clock Generation design, employing a tri-state connection and logic gate, demonstrates superior power savings, even when applied to the target module. This approach optimizes power efficiency in digital design while proving particularly effective in reducing dynamic power within logic circuits. Implementing an improved gate-based clock gating technique in ALU design, our results show a noteworthy reduction in clock delay (71% to 78%), a 23% improvement in area, and a substantial 66.67% enhancement in power efficiency. Notably, this clock gating scheme surpasses alternative methods in terms of area requirements. The experiments, exclusively conducted on ALU design, utilized 130 nm standard logic libraries for implementation. The design architecture was meticulously crafted using Verilog HDL, and simulations were executed with ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.
... Another lossless approach is proposed based on Huffman coding for text compression. This approach is also implemented on FPGA for validating the working of the proposed algorithm [9]. In [10], run-length coding and delta coding-based compression technique is proposed for compressing medical data with improved compression ratio. ...
Due to the increase in the growth of data in this era of the digital world and limited resources, there is a need for more efficient data compression techniques for storing and transmitting data. Data compression can significantly reduce the amount of storage space and transmission time to store and transmit given data. More specifically, text compression has got more attention for effectively managing and processing data due to the increased use of the internet, digital devices, data transfer, etc. Over the years, various algorithms have been used for text compression such as Huffman coding, Lempel-Ziv-Welch (LZW) coding, arithmetic coding, etc. However, these methods have a limited compression ratio specifically for data storage applications where a considerable amount of data must be compressed to use storage resources efficiently. They consider individual characters to compress data. It can be more advantageous to consider words or sequences of words rather than individual characters to get a better compression ratio. Compressing individual characters results in a sizeable compressed representation due to their less repetition and structure in the data. In this paper, we proposed the ArthNgram model, in which the N-gram language model coupled with arithmetic coding is used to compress data more efficiently for data storage applications. The performance of the proposed model is evaluated based on compression ratio and compression speed. Results show that the proposed model performs better than traditional techniques.
... So, it deeds as an out-of-doors circuited route [13]. This could make sure that Huffman modules cognitive manner, handiest one module is chosen at a time and carried out, while the relaxation of cognitive procedure are in tri-nation [14]. Figure 5 shows Power Management Control (PMC) validation. ...
Clock gating is a very important technique for decreasing wasted power in digital design. One of the approaches to obtain dissipated power is an intention by the way of masking the clock pulse that is going to the unused part of the design. In this research, a comparative evaluation of current clock gating techniques on synchronous digital design changed into provided. In the new suggested design, the gated clock technology circuit is a use of tri-state buffer and gated clock. The new submodule was created by the connection of two tri-state logic used as switched to control to the design. The new suggested technique was saving more power and area. The suggested sub-module was achieved by using ASIC design methodologies. In order to implement Huffman modules, the architecture of the proposed module has been generated using Verilog HDL language. In addition, it is proved using Modalism-Altera 10.3c (Quartus II 14.1) tools. By using the tri-state technique, dynamic power and total power are decreased. The suggested technique will decrease the hardware complexity.
... This source coding procedure declines bits quantity in the information once it equaled to the ASCII demonstration of the sequence [4]. Text coding is an application of information confining that encrypts the initial paragraph using several parts [5]. Purpose of information compression is to decrease repetition of the document in order to hold or send a special through a beneficial method [6]. ...
Huffman coding is very important technique in information theory. Compression technique is the technology for reducing the amount of data used to denote any content without decreasing the quality. Furthermore, Clock gating is an effective method for decreasing power consumption in a sequence design. It saves more power by dividing the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. This paper aim to design Huffman coding and decoding process with proposing a novel method of clock gating to achieve low power consumption. Huffman design is executed by expending ASIC design procedures. With the purpose of executing the encoder and decoder structures, 130 nm typical cell technology libraries are utilized for ASIC implementation. The simulations are completed by utilizing Modelsim tool. The design of coding and decoding process has been made using Verilog HDL language. Moreover, it carried out using Quartus II 14.1 Web Edition (64-Bit).
... At present, there are only limited publications on accelerating compression and decompression for Huffman codecs using specific hardware platforms [8,9]. Our proposal distinguishes from these work as our design explores software and hardware co-design and is aimed at building a generic decompression architecture. ...
... Therefore, a huge amount of data is typically produced and measured, especially when the long lifetime of a structure is monitored. However, most successful compression techniques developed in SHM, including wavelet-based compression techniques [2,3], Huffman lossless compression technique [4], and other compression schemes that rely on the application of a transform is inherent wasteful because of the Nyquist-Shannon theorem requirement to first acquire a full data set and then compute the transform for data compression. ...
Bayesian compressive sensing (BCS) has provided algorithms to reconstruct underlying signals from far fewer compressed measurements by adopting the theory of sparse Bayesian learning (SBL). However, BCS lacks robustness when the number of measurements is much less than the length of the original signal because signal reconstruction accuracy is sensitive to the specific compressed measurements. As a result, signal reconstruction diagnosis and accuracy enhancement are necessary to tackle this problem. In this study, multi-task SBL is introduced for robust diagnosis and 'healing' of BCS signal reconstruction. A diagnosis technique is proposed to investigate whether the reconstructed (decompressed) signal representation is accurate, based on the phenomenon that inaccurate (suboptimal) signal models are much less stable than accurate (optimal) ones. For accuracy enhancement of compressive sensing signal reconstruction, a modified two-task learning algorithm is developed for potentially improving BCS reconstruction, and the corresponding 'healing' method is presented combined with the diagnosis technique. By applying these methods, the performance of BCS signal reconstruction can be monitored and, when necessary, improved. The real data collected from the structural health monitoring system of a bridge show that the accuracy of BCS reconstruction for automated recovery of data lost during wireless transmission is significantly enhanced by the proposed diagnosis and 'healing' methods.
... This source coding procedure declines bits quantity in the information once it equaled to the ASCII demonstration of the sequence [4]. Text coding is an application of information confining that encrypts the initial paragraph using several parts [5]. Purpose of information compression is to decrease repetition of the document in order to hold or send a special through a beneficial method [6]. ...
Huffman coding is very important technique in information theory. Compression technique is the technology for reducing the amount of data used to denote any content without decreasing the quality. Furthermore, Clock gating is an effective method for decreasing power consumption in a sequence design. It saves more power by dividing the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. This paper aim to design Huffman coding and decoding process with proposing a novel method of clock gating to achieve low power consumption. Huffman design is executed by expending ASIC design procedures. With the purpose of executing the encoder and decoder structures, 130 nm typical cell technology libraries are utilized for ASIC implementation. The simulations are completed by utilizing Modelsim tool. The design of coding and decoding process has been made using Verilog HDL language. Moreover, it carried out using Quartus II 14.1 Web Edition (64-Bit).
Data compression using Huffman coding refers to decreasing the quantity of data without decreasing the quality of original file. Besides that, it can retrieve original data in decompression process without losing any details. In this research, an 9bit/8bit encoding and decoding process divide the block design. The input transmission code consists of 9-bit which are variable in length coding and can be suitable for high-speed applications. Coding and decoding blocks were designed separately. The encoder module gets the 9-bit data used as input and delivers the 8-bit coded-output from encoder design. this output data used as input to the decoder module to get the 8-bit as output form decoder design. In this research, the proposed design includes encoder and decoder were achieved Compression Ratio up to 52% from original data size and saving percentage up to 47.95%. The suggested design was implemented by using ASIC and FPGA design methodologies to execute the compression and decompression architectures. The architecture of coding and decoding process has been created using Verilog HDL language. Quartus II 11.1 Web Edition (32-Bit). In addition, simulated using ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition. And it is implemented using Altera FPGA (DE2) for real time implementation. Finally, all of the blocks were combined together to have an integrated system.
Data compression using Huffman coding refers to decreasing the quantity of data without decreasing the quality of original file. Besides that, it can retrieve original data in decompression process without losing any details. In this research, an 9bit/8bit encoding and decoding process divide the block design. The input transmission code consists of 9-bit which are variable in length coding and can be suitable for high-speed applications. Coding and decoding blocks were designed separately. The encoder module gets the 9-bit data used as input and delivers the 8-bit coded-output from encoder design. this output data used as input to the decoder module to get the 8-bit as output form decoder design. In this research, the proposed design includes encoder and decoder were achieved Compression Ratio up to 52% from original data size and saving percentage up to 47.95%. The suggested design was implemented by using ASIC and FPGA design methodologies to execute the compression and decompression architectures. The architecture of coding and decoding process has been created using Verilog HDL language. Quartus II 11.1 Web Edition (32-Bit). In addition, simulated using ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition. And it is implemented using Altera FPGA (DE2) for real time implementation. Finally, all of the blocks were combined together to have an integrated system.
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