Kamran Eshraghian

iDataMap Corporation Pty Ltd

The development of a bioinspired image sensor, which can match the functionality of the vertebrate retina, has provided new opportunities for vision systems and processing through the realization of new architectures. Research in both retinal cellular systems and nanodriven memristive technology has made a challenging arena more accessible to emula...

Existing computational models of the retina often compromise between the biophysical accuracy and a hardware-adaptable methodology of implementation. When compared to the current modes of vision restoration, algorithmic models often contain a greater correlation between stimuli and the affected neural network, but lack physical hardware practicalit...

The packing density associated with crossbar arrays offers important architectural solutions to numerous forms of computational engines. Mitigation of sneak paths in the crossbar array, however, requires additional layers in fabrication technology to impede current flow in order to avoid undesired changes to the state when reading and writing to an...

Our visual processing system is remarkably good; the retina is nothing like the CMOS image sensor, or for that matter, any of the vision processing architectures that have driven vision systems research for over three decades. Therefore, before embarking upon the complex task of architectural mapping of the retina into hardware, it is essential to...

With the advent of memristor-CMOS (MCM) process that combines CMOS processing with nano-scale memristive devices, it becomes possible to reduce utilization of silicon area thus providing a promising option in the design of MCM based circuits. Two properties of memristor have attracted the most attention. Firstly its nanometer scale dimensions and,...

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area o...

This paper presents a memristor-CMOS based RBSD adder. Conventional RBSD adders suffer bigger hardware due to the extra logic handling larger number of bits. The purpose of this paper is to improve the silicon surface area and the computation delay of conventional RBSD adders. The proposed method employs memristor-CMOS based circuit. The implementa...

Nanoscale memristive structures realized through combination of metal–insulator–metal (MIM) processing technologies have paved the way for efficient adoption of memory constructs such as ReRAM crossbar essential for mapping of new and emerging architectures. A noticeable drawback of the crossbar architecture is the existence of sneak-path currents...

This paper presents a CMOS image sensor(CIS) VLSI architecture based on a single-inverter time-to-threshold pulsewidth modulation circuitry capable of operating as low as 330-mV supply voltage while retaining a signal-to-noise ratio of 24 dB; an important characteristic being demanded by very low voltage portable CIS-based equipment such as disposa...

Hardware multipliers are an essential component of signal processes and related algorithms embedded within numerous multimedia and communication systems. This paper presents memristor-CMOS based reconfigurable multiplier architecture having a variable bit-width computational capability. The approach provides the much needed flexibility in configura...

Sensory search engines in a variety of applications, including DNA sequencing, are beginning to influence the way new search nanoarchitectures are constructed. This paper presents a novel nanoarchitecture based on a complementary resistive switch (CRS) construct for smart sensor search engines. Detailed operational principles of CRS, CRS-based memo...

The missing link between a nonlinear circuit element that is able to self-adjust its conductance according to the history of applied voltage/current and physical realizations of two-terminal oxide-based resistive memory was discovered in early 2008, and has since been intensively studied. This class of memory elements is called memristive devices,...

The crosstalk in CMOS photodiodes has been measured, at two wavelengths of 543 and 633 nm, by an experimental structure containing several types of photodiodes with varying dimensions. The role of the design of the junction in reducing crosstalk is studied. The measurements indicate that to reduce crosstalk it is essential to optically shield the g...

This paper introduces an integrated sensor circuit based on an analog Memristor-MOS (M2) pattern matching building block that calculates the similarity/dissimilarity between two analog values. A new approach for a pulse-width modulation pixel image sensor compatible with the memristive-MOS matching structure is introduced allowing direct comparison...

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Me...

Resistive memory (RRAM) is based on two-terminal resistive switches whose states can be reconfigured with external pulses. RRAM has attracted significant interest recently as a promising candidate for future high-density, high-performance memory applications. Memristors hold promise for use in diverse applications such as memory, logic, analog circ...

Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we ad...

This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel arr...

The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applica-tions. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some...

As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nano-features and unique $I$-$V$ characteristics...

This paper provides new approach for nonvolatile Memristor-based Content Addressable Memory MCAM cell using memristor with CMOS processing technology in order to get high speed read/write operations within high packing density and low power dissipation. The proposed cell uses only two memristors as a memory cell and CMOS controlling circuitry which...

This paper provides new approach for nonvolatile Memristor-based Content Addressable Memory MCAM cell using memristor with CMOS processing technology in order to get high speed read/write operations within high packing density and low power dissipation. The proposed cell uses only two memristors as a memory cell and CMOS controlling circuitry which...

The nanometer scale feature of memristor created a broad range of opportunities for innovative architectures. The nature of the boundary conditions, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces new challenges in modeling, characterization, and measurements for Memristor-MOS (M<...

We present new computational building blocks based on memristive devices. These blocks, can be used to implement either supervised or unsupervised learning modules. This is achieved using a crosspoint architecture which is an efficient array implementation for nanoscale two-terminal memristive devices. Based on these blocks and an experimentally ve...

This paper presents a novel resistive-only Binary and Ternary Content Addressable Memory (B/TCAM) cell that consists of two Complementary Resistive Switches (CRSs). The operation of such a cell relies on a logic$\rightarrow$ON state transition that enables this novel CRS application.

This paper presents the implementation of a 3-D architecture for a biomedical-imaging system based on a multilayered system-on-system structure. The architecture consists of a complementary metal-oxide semiconductor image sensor layer, memory, 3-D discrete wavelet transform (3D-DWT), 3-D Advanced Encryption Standard (3D-AES), and an RF transmitter...

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new in...

The convergence of significantly different and disparate technologies such as spintronics, carbon nano tube field effect transistors, photon and bio-responsive molecular switches, memristor and memristive systems and metamaterials, coupled with energy scavenging sources are gaining a renewed focus in the quest for new products. This paper will prov...

Large-capacity Content Addressable Memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more...

In 2008, researchers at HP Labs published a paper in {\it Nature} reporting the realisation of a new basic circuit element that completes the missing link between charge and flux-linkage, which was postulated by Leon Chua in 1971. The HP memristor is based on a nanometer scale TiO$_2$ thin-film, containing a doped region and an undoped region. Furt...

This paper presents a three-dimensional discrete wavelet transform (DWT) for image processing based on unary arithmetic. The upper layer on-chip camera provides the input to the lower 3D-DWT processor layer utilizing Through Silicon Via (TSV) interconnections technology for data and signal transfers. Stacking of chips allow for low power operation...

Improving cryptographic system security and integrity against side channel attacks have attracted significant attention by researcher during the last two decades. This paper presents Globally Asynchronous Locally Synchronous (GALS) based block cryptographic algorithm as part of a approach in the design of an asynchronous cryptographic system in ord...

Advances in system on chip (SoC) and system in package (SiP) that draw upon experiences gained from nano, bio and photon based technologies have created a new domain that permits fabrication of multiplicity of independent technologies as part of 3D hyper-integrated system on system (SoS) platform. Recent advances in nonlinear optics supported by fa...

This paper presents a 3D approach towards the implementation of a bio-medical image capture and encryption system that can be implemented as a core of portable medical devices for image capture and secure transmission. The multilayered System-on-System (SoS) architecture comprises CMOS imager, memory, 3D-DWT, 3D-AES and an RF transmitter layer. Chi...

This paper presents a low power and high speed 3D-DWT (three-dimensional discrete wavelet transform) architecture using stacked silicon dies for image compression of medical images. The interconnections of stacked chips are based on TSV (through silicon via) techniques. Its low power operation is due to short signal paths between layers. The area o...

This paper presents an integrated approach towards a multilayered architecture based upon stacked silicon dies for image capture and secure image transmission. The System-on-System approach presented comprises CMOS imager, memory, 3-D DWT, 3-D AES and RF transmitter layer. Chips fabricated by different processes are stacked and interconnected using...

New developments in nanoelectronics are promising a new generation of computing, which has greater focus on device capabilities. Further to many applications of memristors in artificial intelligence or artificial biological systems, they enable reconfigurable nanoelectronics and also provide new paradigms in application specific integrated circuits...

Convergence of significantly different and disparate technologies such as spintronics, memristor and memristive systems, carbon nano tube field effect transistors (CNFET), metamaterials, photon and bio-responsive molecular switches, coupled with energy scavenging sources are gaining a renewed focus in the quest for new products. The inevitability o...

This paper presents an integrated approach towards implementation of a multilayered architecture based upon stacked silicon for image capture and secure data transmission suitable for bio-medical devices and implementation within patient-point-of-care network. The system architecture is comprised of a CMOS based image sensor layer, memory layer, 3D...

The science fiction of yesterday depicted by such characters as Captain Kirk of the space ship Enterprise has stretched the minds of researchers that no longer scaling of feature size predicted by Gordon Moore is seen to adequately provide the necessary technology direction. While ITRS is driving the search for fabrication solutions inexorably clos...

Although silicon technology is continuously evolving to produce smaller systems with minimized power dissipation and at a lower cost and improved reliability, it is expected that this trend will have matured between 2014 and 2016. This will eventually lead to the integration of a multiplicity of technologies rather than simply silicon technology. T...

This research shows a 1mW Low Power and real-time imaging Tx/Rx communication system via RF-delay smart Antenna using up to 10GHz UWB(Ultra WideBand) as a concept of Wireless Medical Telemetry Service (WMTS). This UTCOMS (COMmunication System for Nano-scale USLI designed Endoscope using UWB technology) results in less body loss(about 6~13dB) at hig...

This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D) vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable arra...

This paper describes the high-level system modeling and functional verification of a novel 3D vertically integrated Adaptive Computing Systemon- Chip (ACSoC), which we term 3D-SoftChip. The 3D-SoftChip comprises two vertically integrated chips (a Configurable Array Processor and an Intelligent Configurable Switch) through an Indium Bump Interconnec...

In this paper, an integrated optical beam router for MicroPhotonic switching is described. The router employs a piecewise linear optic that steers and couples optical collimated beams to optical fiber ports with minimum loss. Experimental results show that for a 3-port MicroPhotonic switch, fiber-to-fiber optical coupling loss less than 0.5 dB and...

In this paper, we discuss the use of MicroPhotonic processors to control the optical power distribution in photonic signal processing structures, achieving adaptive photonic RF filtering with arbitrary transfer functions. A new MicroPhotonics-based photonic signal processing architecture is presented, in which fibre collimator arrays, Opto-VLSl pro...

This paper presents an optimum phase design implementing a 256 phase beam steering (BS) Opto-ULSI processor (OUP) for multi-function capable optical networks. The world smallest 9um × 9um optical mirror cell to develop an initial 8 phase Opto-ULSI processor that implements a 256-phase BS OUP for integrated intelligent photonic system (IIPS) is to p...

In this paper, we describe a novel Reconfigurable MicroPhotonic Add/Drop Multiplexer (RMPADM) using a reconfigurable Opto-VLSI processor to simultaneously steer many WDM channels hence accomplishing add/drop multiplexing. A 4-WDM-channel RMPADM structure is experimentally demonstrated. Results show that single and/or multiple add/drop multiplexing...

The method for the multi-phase computer-generated-holography (CGH) design of reconfigurable chip or board level optical interconnection is discussed in this paper. First, an improved direct search (DS) algorithm for the multi-phase CGH design is presented. Using this method, the high quality multi-phase CGH can be calculated very quickly, and the c...

The characterization of photodiode junction depth using laser beam induced current (LBIC) has long been ambiguous, due in part to the limited understanding behind the relevant physics governing this phenomena, and more importantly, the signal behavior for the various device geometries. In this work, the induced current behavior arising from the ind...

A novel tunable optical filter structure based on an Opto-VLSI processor is proposed in this paper. The architecture is capable of dynamically tuning multiple pass-bands through reconfiguration of the size and shape of holographic diffractive gratings generated by the Opto-VLSI processor. Results for an experimental 3-passband tunable filter are pr...

MicroPhotonic broadband RF signal processors utilize the capability of photons to perform true-time delay processing at very low loss that is unattainable by conventional electronic methods. In this paper, we present a novel MicroPhotonic interference mitigation filter architecture that utilises a CMOS Si photoreceiver/VCSEL array in conjunction wi...

With the increasing demand on the access network in the local and residential areas, there is a growing need for more scalable and dynamic optical access network architectures. In this paper, variable optical splitter is utilized in the optical access network as branching device. By changing the number of branches at the variable optical splitter o...

A novel tunable optical filter structure based on an Opto-VLSI processor is proposed in this paper. The architecture is capable of dynamically tuning multiple pass-bands through reconfiguration of the size and shape of holographic diffractive gratings generated by the Opto-VLSI processor. Results for an experimental 3-passband tunable filter are pr...

In 1959, the physicist Richard Feynman advised his colleagues that "there's plenty of room at the bottom." He envisioned a discipline devoted to manipulating smaller and smaller units of matter. "I am not afraid," he wrote, "to consider the final question as to whether, ultimately -- in the great future -- we can arrange the atoms the way we want,...

This paper presents the test and validation of FPGA based IP using the concept of remote testing. It demonstrates how a virtual tester environment based on a powerful, networked Integrated Circuit testing facility, aimed to complement the emerging Australian microelectronics based research and development, can be employed to perform the tasks beyon...

MicroPhotonic broadband RF signal processors utilize true-time-delay methods to perform processing functions that cannot be achieved by conventional electronic methods. In addition to their small physical size and immunity to EMI, Photonic signal processors offer the possibility of delaying broadband RF signals with almost no loss. In this paper, w...

This paper describes the transmitter chip and system of Code Division Multiple Access (CDMA) for measurement of electric field intensity. The transmitter chip and system of CDMA is also designed in compliance with IS-95C standard of the Telecommunications Industry Association and the Electronic Industries Association (TIA/EIA/IS-95)and Internationa...

In this paper, we propose the integration of Opto-VLSI systems and photonic components to realise a reconfigurable MicroPhotonic add/drop multiplexer (RMPADM) that can scale to tens of Wavelength Division Multiplexed (WDM) channels while maintaining low insertion loss and low crosstalk. We demonstrate the proof-of-principle of a 2-WDM-channel RMPAD...

An efficient wavelength division multiplexed (WDM) channel equalizer employing a dynamic MicroPhotonic processor is demonstrated. Using a proof-of-principle 6-channel equalizer setup, optimum phase holograms have been generated, which realise WDM equalisation with more than 25 dB dynamic range and less than 0.2 dB power ripples.

This project investigates an optimum phase design implementing a 256 phase Opto-ULSI processor for multifunction capable optical networks. The design of an 8 phase processor is already in construction and will provide the initial base for experimentation and characterization. The challenge is to be able to compensate for the non-linearity of the li...

We propose a novel multiband tunable optical filter structure based on an Opto-VLSI processor. Tunability for each band is achieved by controlling the size and shape of holographic diffractive grating generated on the Opto-VLSI processor. Results for an experimental 3-passband tunable filter are presented indicating over 25 dB of dynamic range and...

Opto-VLSI processors offer promising technological platform for implementing reconfigurable Wavelength Division Multiplexing (WDM) networks. By driving an Opto-VLSI processor with a computer generated hologram (CGH), dynamic optical beam steering and/or multicasting can be achieved. In this paper we develop and compare CGH algorithms based on simul...

A novel architecture for a microphotonic beamformer that generates variable RF true-time delays to steer broadband s for smart antennas, is presented. The beamformer employs a Vertical Cavity Surface Emitting Laser (VCSEL) array, photoreceiver array, and micro-optics integrated on an optical substrate through which many delayed versions of the RF a...

In this paper, a novel integrated optical beam router for microphotonic switching is presented. The router uses a piecewise linear optic that steers and couples optical collimated beams to optical fibre ports with minimum loss and excellent tolerance to fluctuations in design parameters. Experimental results show that for a 1×2 MicroPhotonic switch...

CMOS imaging arrays in back-illuminated mode provide a means to realize photodiode arrays for high resolution imaging systems, provided crosstalk effects can be reduced to the level of those observed in front-illuminated arrays. In this study, we have simulated the crosstalk in back-illuminated and front-illuminated arrays as a function of differen...

We demonstrate an efficient wavelength-division-multiplexed (WDM) equalizer structure that uses a reconfigurable opto-very large scale integrated processor to steer/reshape many optical beams simultaneously, thus, achieving channel-by-channel equalization. The opto-VLSI processor consists of an array of liquid crystal (LC) cells independently addre...

A novel Opto-VLSI multiband tunable optical filter structure is proposed and demonstrated. Filter tunability is achieved by reconfiguring the holographic diffraction grating of an Opto-VLSI processor, allowing multiple passbands to be independently synthesised. A proof-of-principle three-passband tunable filter of 2 nm bandwidth is experimentally v...

Mobile multimedia communication has rapidly become a significant area of research and development constantly challenging boundaries on a variety of technological fronts. The processing requirements for the capture, conversion, compression, decompression, enhancement, display, etc. of increasingly higher quality multimedia content places heavy deman...

Standard CMOS fabrication processes provide the means to realize the further development of back illuminated photodiode arrays for imaging systems. We have simulated crosstalk effects in a back illuminated CMOS compatible photodiode array, and compared this effect with that predicted for front illuminated arrays, using a two dimensional simulation...

An Opto-VLSI system implementation for 4G Mobile Communication Service (MCS): Image Processor with Optical Space Switch that is capable of switching a large number of input and output fibers in real time is presented. A reconfigurable network may offer bandwidth on demand by configuring itself to optimize for the traffic bottlenecks. The image proc...

In this paper, the capability of Opto-VLSI processors to generate reconfigurable diffractive gratings is utilised to efficiently control the optical power distribution in photonic signal processing structures, achieving photonic RF bandpass filtering with arbitrary transfer functions. A new OptoVLSI- based photonic signal processing architecture th...

In this paper we propose an on-pixel Analogue-to-Digital Converter (ADC) based on pulse frequency modulation (PFM) scheme. This PFM based converter presents a viable solution for pixel-level based ADC. It uses a simple and robust circuit that can be implemented in a compact area resulting in a 23% fill-factor for a digital vision sensor in 0.25 μm...

Mobile multimedia communication has rapidly become a significant area of research and development. The processing requirements for the capture, conversion, compression, decompression, enhancement, display, etc. of high quality multimedia content places heavy demands even on current ULSI (ultra large scale integration) systems, particularly for mobi...

The Australian Commonwealth government recently announced a grant of $4.75 million as part of a $13.5 million program to establish a world class networked IC tele-test facility in Australia. The facility will be based on a state-of-the-art semiconductor tester located at Edith Cowan University in Perth that will operate as a virtual centre spanning...

In this paper we propose an on-pixel Analog-to-Digital converter based on pulse frequency modulation (PFM) scheme. This PFM based converter presents a very viable solution for pixel level based ADC. It uses a very simple and robust circuit that can be implemented in a compact area resulting in a 23% fill-factor. The low-light performance of the PFM...

In the span of a few years, mobile multimedia communication has rapidly become a significant area of research and development constantly challenging boundaries on a variety of technological fronts. Video compression, a fundamental component for most mobile multimedia applications, generally places heavy demands in terms of the required processing c...

Camera-on-a-CMOS chip will be an inevitable component of future intelligent vision systems. However, up till now, the dominant format of data in imaging devices is still analog. The analog photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. Moreover, in the active pixel configuration the area occupied by circ...

The Australian Commonwealth government recently announced a grant of $4.75 million as part of a $13.5 million program to establish a world class networked IC tele-test facility in Australia. The facility will be based on a state-of-the-art semiconductor tester located at Edith Cowan University in Perth that will operate as a virtual centre spanning...

Layer assignment is an important post-layout optimization technique in very large scale integrated circuit (VLSI) layout automation. It re-assigns wire segments in a routing solution to appropriate layers to achieve certain optimization objectives. The paper focuses on investigating the layer assignment problem with application to via minimization,...

In this paper we propose an on-pixel Analog-to-Digital converter based on pulse frequency modulation (PFM) scheme. This PFM based converter presents a very viable solution for pixel level based ADC. It uses a very simple and robust circuit that can be implemented in a compact area resulting in a 23% fill-factor. The low-light performance of the PFM...

In this paper, a CMOS circuit for flexible read-out of imagers is proposed allowing random access, sequential access and window based access to the pixels. The circuit has been implemented within a CMOS imager using 0.7 micrometers technology. It is shown that this versatile read-out technique is obtained with only 8% increase in the silicon area a...

We propose a parallel architecture for the implementation of the embedded zerotree wavelet (EZW) algorithm, based on the depth-first search (DFS) bit stream (BS) architecture. Using the depth-first search of the wavelet coefficient tree, the wavelet coefficients in the coefficient tree are first partitioned into independent sub-trees. In the case o...

In this paper, we present a dataflow-oriented architecture for a modified SPIHT algorithm which is suitable for VLSI implementation. The input into the architecture is a bit stream of the wavelet coefficients in the depth-first search (DFS) format and the output from the architecture is a data stream containing the significance map (MAP) and succes...

In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performanc...

The new generation of personal interactive mobile multimedia mobile communication (M³C) demand highly compact low power devices capable of image capture and display as well as low bit rate coding and transmission. The new design concept based upon integration of optics with that of electronics has facilitated the realisation of a novel i...

A backside illuminated CMOS photodiode consisting of an n+ (source implant) emitter and P-substrate base has been numerically simulated in a 1D approximation. The effects of device dimensions (junction depth and photodiode thickness), emitter and base dopant concentrations have been examined in relation to the spectral dependence of the quantum eff...

The concept of "technology generation" attributed to Gordon Moore has created a plausible method for predicting the behavior of technology road map that has seen world's production of silicon CMOS to exceed 75% of electronic related materials. A feature of such progress is characterized by the complexity factor that predicts the emergence of a new...