Test Structure Design Considerations for RF-CV Measurements on Leaky Dielectrics

Abstract

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm². The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

Full text

Test Structure Design Considerations for
RF-CV
Measurements on Leaky Dielectrics
J.
Schmitz*,
F.
N.
Cubaynest,
R.
J.
Havenst,
R.
de
Kortt,
A.
J.
Scholtent and
L.
F.
Tiemeijerl
'Philips Research Leuven; Presently
at
the University of Twente, The Netherlands. Email: J.Schmitz@utwente.nl
tphilips Research Leuven, Kapeldreef
75,
3001
Leuven, Belgium
tPhilips Research Laboratories, Prof. Holstlaan
4,
5656AA Eindhoven, The Netherlands
Abstract- We present
a
MOS
Capacitance-Voltage mea-
surement methodology that, contrary
to
present methods, is
highly robust against gate leakage current densities
up
to
1000
A/cm2.
The methodology features specially designed
RF
test structures and
RF
measurement frequencies. It allows
MOS
parameter extraction
in
the full range
of
accumulation,
depletion
and
inversion.
I.
Introduction
As
CMOS
device dimensions are scaled below
100
nm,
the concurrent gate dielectric thinning leads to pro-
gressively higher gat,e leakage currents. Tunnel current
densities around
100
A/cm2 are foreseen for the near
future in some
CMOS
logic applications
[l].
Although this
may be acceptable from
a
functional point
of
view, such
leakage currents complicate fundamental
MOS
characteri-
zation techniques like charge pumping
[Z],
time-dependent
dielectric breakdown tests
131
and capacitance-voltage
(C-
V)
measurements
[4-81.
Gate leakage affects the measurement of the
capacitance-voltage characteristic
as
well
as
its
interpretation This can be understood conceptually
by considering
a
simple three-clement equivalent circuit
for the leaky
MOS
capacitor
as
sketched in Fig.
1.
The
capacitance
C
is
connected in parallel
to
a
(strongly
Fig.
1.
MOS
capacitor.
Threeelement
equivalent
circuit
approximation
of
a
leaky
(2)
Q
5
-I
m(z)
=
wc
g
+
R(w2CZ
+
g2)
Re(Z)
The quality factor determines to
a
large extent if
a
capacitance measurement
at
angular frequency
w
=
Zsf
will yield an accurate value. When
Q
>
10,
capaci-
tance meaurement and analysis
is
straightforward. For
1
<
Q
<
10,
careful analysis (with quantification of the
parasitic contributors
g
and
R)
can still yield
a
good
value of the capacitance, provided that
a
good model
is
used; the three-element approximation
of
Fig.
1,
used here
for
a
qualitative illustration,
has
its limitations
[6,8].
For
Q
<
1,
the instrument precision
is
spent on accurate de-
termination
of
(one of) the resistive components,
and
the
measurement of the imaginary part becomes inaccurate.
The quality factor rises linearly with frequency in
the low-frequency range, reaches
a
maximum
QOpt
at
frequency
fopt,
and then drops linearly with frequency
as
sketched in Fig.
2.
Taking
6Q/aw
=
0
in equation
(2)
I
I
0.1
10'
IO'
10'
10'
10"
I
frequency
(Hz)
bias-dependeot) differential conductance
g
z
dI/dV
arising
from
gate
current,
An
external
resistance
originating e.g. from gate resistance,
is
also inevitable.
The impedance
2
of this three-element circuit and the
related quality factor
Q
can be expressed
as
Fig.
2.
Frequency
dependence
of
the
quality
factor
Q
of
the
three-
element
circuit
sketched
in
Fig.
1.
Far
this
example,
C
=
2
pF,
=
50~10-6
R-1,
and
R
=
IO
R.
yields the following expressions for
QOpt
and
fopt:
1
fop1
=
"rm
(3)
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02003
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1
=
243qiT33
(4)
As
long
as
the measurement instrument limitations (preci-
sian, frequency range)
do
not
play arale, ameasurement
at
fopt
will lead to the most accurate value for
C.
To
obtain
Qopt
>
1,
it
follows directly from (4) that
R
should satisfy
gR<
-
w0.2
2
(5)
This equation shows that the higher the gate leakage (and
hence g), the lower the external resistance
R
must be. This
is
an
important design criterion for RF-CV test structures,
as
further discussed in the next Section.
When
Qopt
>
1,
the quality factor
Q
is above unity
in
a
frequency range around
fopt.
This frequency range
is defined by the minimum measurement frequency
fmin
and the maximum frequency
ftop,
as
indicated in Fig.
2.
Expressions for
fmin
and
ftop
can he readily derived from
solving
Q
=
1 in
(2):
(6)
1
-
\/1-4gR(l+gR)
g
R5-
47rRC
27rc
fmin
=
(7)
1
+
d1- 4gR(1+ gR)
1
w-
47rRC 27rRC
ftop
=
The minimum frequency is dictated by the magnitude
of
the gate leakage g. Typical MOS capacitors
as
studied in
present research and development work suffer from gate
leakage to such an extent that measurements in the normal
LCR
range
of
1
kHz
-
1
MHz
are inadequate. For example,
a
lox
10
pmZ
MOS
capacitor with 10 A/cmZ gate leakage
typically has
C
=
2
pF, g
=z
50x
lo-'
W',
and R
=
10-
100
R
leading to
fmjn
=
4
MHz.
As
Q
will rise linearly
with
f
above
fmin,
a
good C-V measurement
on
such
a
device is best conducted above 10 MHz.
The highest measurement frequency
ftap
is
constrained
by external resistance. When excessive gate leakage forces
the application of
RF
measurement frequencies (following
equation
(6)),
the external resistance must therefore he
reduced to
a
minimum to still allow
a
good measurement
of capacitance.
11.
Test structure design
Conditions
(5)-(7)
dictate the layout of
a
C-V test
structure to
a
great extent. There
is
design freedom in
the choice of device area
and
the external resistance
(influenced e.g. by geometric choices and by impurity
distributions in the substrate). While specific capacitance
and specific conductance are fixed for a given dielectric
(and DC bias), the external resistance in many cases scales
with the square root of area (see e.g. [11],[12]). Therefore,
a
smaller area device will yield an improved
QOpt
as
the
product
gR
decreases. For any reasonable dielectric (with
a
leakage current density below 1 kA/cmZ), the condition
gR
-K
0.2
can he met by
a
careful design
of
the test
structure: abundant, nearby well contacts and
a
small
gate area. (For
a
sufficiently high total capacitance, several
devices with separate well contacts can be connected in
parallel,
as
in
[9].)
Figure
3
shows
a
layout used for
RF
transistors that
fulfills
these requirements. Once a design
0
'..:O.::a
':
o.:n
:.:'U
'
01
0
;:..cl
01
I
I
Ill
U
'
lul
source
Id
'
Id1,
;a..'':
0:
,a,.
>o-;:.
U.
;,~
O...F.O'
\we,,
contact
ring
Fig.
3.
Top view
of
the (conceptual) layout
of
an
RF
transistor,
suitable
for
Rl-CV
measurements.
Several
parallel
gates
run
hori-
zontally across
a
rectangular active area.
The
gates
are
connected
at
both ends
(on
field isolation)
to
metal-1, to the
Pan-1
band pad
of
a
ground-signal-ground test Structure. The
sources
are
contacted
to
ground; the drains
to
Part-2.
The entire structure is surrounded by
a
well
connection ring ('guard ring'), connected to ground.
has been created in line with the above considerations,
estimates for
fmjn
and
QOpt
can he made, from which it
can be readily determined if the test structure is suitable
for C-V measurement or not.
111.
Device fabrication and characterization
The experimental study of C-V measurements at giga-
hertz frequencies (RF-CV measurements) is carried out
using transistors designed for tweport RF characteriza-
tion
in
ground-signal-ground configuration. They consist
of many gates connected in parallel, with
a
layout resulting
in very low gate resistance and low well resistance,
as
described in the previous section. Sub-micron channel
lengths are used to suppress channel resistance. The gate
is
connected to Port 1, drain connected to Port
2.
The
gate is biased, all other terminals are grounded.
Devices were fabricated in
a
standard 6-metal
0.12
pm
CMOS flow, and in
a
single-metal CMOS research process.
S-parameter measurements in the range 0.148
GHz
were
carried out on-wafer using an
HP
8510C
network analyzer.
The measurements were accompanied by SOLT calibration
and open-short de-embedding [lo].
IV. Validation
of
RF-CV measurements
Capacitance-voltage measurements between
0.5
and
10 GHz are shown in Fig. 4. Here, Cg8=Im(Yi1)/u, which
is
only
a
good approximation of the
MOS
capacitance
C
when the external resistance R
is
negligible. At the lowest
frequencies, the shape of the curve is
as
expected, with
the accumulation behavior
of
an ultra-thin dielrictric and
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10GHz
0.6
v
0.21
0.0
-3
-2
-1
0
1
2
3
gate
voltage
(V)
Fig.
4.
Left: capacitance-voltage
curve
of
a
W/L
=
384
am/O.l8
pm
NMOS
RF transistor
as
measured
at
various
frequenciea, after de-
embedding.
inversion capacitance decreasing due
to
gate depletion.
The depletion region around
V,
=
0
V shows only
a
moderate decrease in capacitance because this is
a
sub-
micron channel device with significant gate-drain overlap
capacitance.
At
frequencies above
1
GHz,
we observe
a
drop
in
the
capacitance at accumulation bias. It
is
accompanied by a
downward bend of the real part of
YII:
see Fig.
5.
This
I
111111
I
IIIII
IO'
3.10'
IO9
3.109
10"
frequency
(Hz)
Pig.
5.
Real
and imaginary pans of
YII
as
a
function
of
frequency
at
V,
=
-2.5
V,
for
the
measwement~
shown in
Figure
4.
The dashed
line
shows
a
straight-line extrapolation (corresponding
to
a
capacitor
without
series
resistance),
to
guide the
eye.
is not due to a drop in the MOS capacitance, hut rather
the signature
of
a significant external series resistance.
The origin is the well resistance
&.I,,
which results in
a
limited response time
of
bulk holes;
see
Fig.
6.
In this
figure, we have explicitly separated the overlap regions,
with capacitance
CO,
and conductance
gov,
from the
1
Ground
J
Fig.
6.
Cmss
section
of
a
capacitor
(or
transistor), with
an
approximated equivalent CirCuit
in
accumulation.
All
components
in
this
diagram
are
hias
dependent except
RSD
and
&I,.
intrinsic or "channel" region with capacitance
Ci,,,
and
conductance
9intX.
In
accumulation and depletion, charging
and discharging
of
CinLr
requires holes to move from the
"channel" region to the ground connection through
RWeii.
This transport is limited by the characteristic delay time
T
=
which implies (in line with (7)) that the
measurement frequency
f
is restricted to
For the transistor under study,
T
zz
20
ps.
As
a
result
the depletion and accumulation capacitances
of
Ci,t,
are
attenuated
at
frequencies above
1
GHz.
The observed gate capacitance does not drop entirely
to zero due to this series resistance effect, because
of
the
overlap capacitance; and also, because the small signal can
pass to Port 2 via
Cint,
and the junction capacitance
Cj.
In other words, the holes required
to
charge and discharge
Gin,,
can also be supplied from the junction capacitance.
Altogether, it is
far
from trivial to determine
RWd
directly
from these measurements because the small signal applied
to the gate can follow several paths to ground. Instead,
sincc tbc C-V measurements
at
5
1
GHz
are
unaffected
by
T,
Cjnt,
is
best
derived from those measurements.
For this purpose we measured the Y-parameters of two
devices with equal design except
for
the gate lengths, being
130
and
180
nm. Etom the difference
of
the obtained
C,,
curves, we can establish the
Cint,
of
a
50
nm channel
segment. The capacitance
of
this segment
is
shown in
Fig. 7. A C-V model can now be fitted to these data
to obtain the required
MOS
parameters.
As
an
example
we fitted
MOS
Model
11
[lS]
over the full curve, also
shown in the figure. Fit values were:
a
flat
band voltage
of -1.07
V,
1.9 nm oxide thickness, an effective gate
doping
NG
=
2.6~10~~ ~m-~, and
a
substrate doping
of 1.7~10'~ (using no other fit parameters). These
values are well in line with the expected values for this
0.12 pm CMOS process.
V. RF-CV and gate leakage
The RF-CV measurement method can cope with
a
large gate leakage current. We fabricated RF transistors
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h
n
E
L
E
ii
v
"
5
0
-3
-2
-I
0
1
2
3
gate
voltage
(V)
Fig.
7.
Area-normalized capacitance
of
a
50
nm
wide channel
segment
as
computed
from
the difference
of
a
130
nm
and
a
180
nm
gate length RF transistor. A
fit
of
MOS
Model
11
(MM11)
to the data
is
also
shown
(see
text). The dashed line symbolizes the (modeled)
invemion capacitance in
case
of
infinitely high gate doping.
with high-leakage dielectrics in
a
research process flow
(based on
0.18
pm CMOS) using
a
different design
of
RF
structures. These devices unfortunately have
a
much higher
&el,CintI
product (by design), preventing
the correct measurement
of
accumulation and depletion
capacitance in the channel. In inversion however,
Rwell
does not play
a
role while the gate leakage current is
at its highest. The external resistance in inversion (being
the sum of gate, channel,
and
source/drain resistances) is
well below
1
n,
which adequately salves the measurement
problems discussed in e.g.
1141.
Fig.
8
shows the measured inversion capacitance.
Ci,,,
gate voltage
(V)
Fig.
8.
Inversion capacitance and gate leakage current density
of
a
high-leakage dielectric.
The
inversion capacitance is correctly
measured
even
when
the gate current density exceeds
1
kA/cm2,
as
confirmed
by the excellent
fit
with
MOS
Model
11.
was obtained from the capacitance difference between a
I
o8
5.10'
IO'
5ld'
frequency
(Hz)
Fig.
9.
Real
and imaginary components
of
the input admittance
of
an
NMOS capacitor in inversion.
The
device has 1872
pm2
gate
area.
The gate bias
was
varied between
0.3
V
and 2.5
V
in
Steps
of
200
mV.
The imaginary Parts almost overlap, but die to the
exponential
increase
of
gate leakage current with
V,,
the
real
part
of
YII
changes drastically.
imaginary and real parts of the input admittance
(91)
and the quality factor
of
a
0.2 pm gate length device,
a
a
function of frequency. The real part of
YIL
is dominated by
the oxide conductance
gox
at
lower frequencies (horizontal
part of the curve) and by the external (differential)
resistance
kXt
at higher frequencies (steeply rising curve).
The external resistance is the sum of gate, channel, and
drain resistances.
As
a
result, when high gate leakage is
present the capacitor quality factor
is
only larger than
unity in
a
frequency band around
1
GHz,
as
illustrated
by Fig.
10.
Note the shape of the quality factor versus
frequency, which matches very well the predicted shape
when
a
simple three-element approximation is used.
10
1
0)
0
1
o8
5108
lo'
5.10'
frequency
(Hz)
1
Pm
and
a
0.2
Ilm
gate length device. (For this to
be meaningful, the threshold voltage difference between
these devices must be limited.)
No
capacitance "roll-off
is observed,
as
a
direct consequence
of
the
GHz
frequency.
This can be seen from Fig.
9.
The figure shows the
Fig.
IO.
in Figure
9.
Capacitor quality factor derived
from
the
measurements
To assess the validity of the obtained
C-V
c:urves for
MOS
parameter extraction, we fitted MOS Model
11
to
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the
data,
with substrate doping, gate doping and oxide
thickness
as
the only free parameters. The
fit
results are
listed in Table
I,
for fits obtained
on
C-V
curves taken
2.1
4.8
0.90
1.35 0.94
1.35 0.95
1.33
0.94
(1.42) (1.15)
at
various frequencies. The obtained values for the fit
parameters are well in line with the expectations for this
process. The MOS Model
11
fit
yields
an
oxide thickness
and gate doping level independent of frequency in the
range
0.2-2
GHz,
while it
fits
poorly outside that region
(due
to
a
low quality factor).
VI. Conclusions
This paper presents the RF-CV methodology, which al-
lows the measurement and analysis
of
capacitance-voltage
curves even in the presence of gate leakage exceeding
1000
A/cm2.
On
the basis of theoretical and experimental
findings, design guidelines are formulated for
RF
capaci-
tors. When these guidelines are followed, the appropriate
Capacitance-Voltage characteristics are obtained around
1
GHz.
Thesc can be used for the extraction of MVS
parameters such
as
(equivalent) oxide thickness, substrate
doping concentration, and gate depletion. Since power
and functionality requirements restrict the gate leakage in
CMOS circuits to typically
5
1000
A/cm2, the presented
methodology
is
well suited for the characterization
of
any
dielectric foreseen in future CMOS technologies.
Acknowledgments
We would like to thank
D.
B.
M. Klaassen, Ronald van
Langevelde, Johan Klootwijk, and W. Kirklen Henson for
fruitful discussions,
and
the IMEC P-line for manufactur-
ing the devices discussed in Section V. This work
was
partly supported by the EC within the framework of the
Artemis project.
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