Junghyup Lee

Queensland University of Technology | QUT · ARC Centre of Excellence for Free Radical Chemistry and Biotechnology

Recent developments in artificial neural networks and their learning algorithms have enabled new research directions in computer vision, language modeling, and neuroscience. Among various neural network algorithms, spiking neural networks (SNNs) are well-suited for understanding the behavior of biological neural circuits. In this work, we propose t...

This paper presents a 46 nF/10 MΩ-range, digital-intensive, reconfigurable RC-to-digital converter (R²CDC) that can readout multiple C and R sensors in a time-interleaved fashion. Ratio-metric conversion using swing-boosted period-modulation (SB-PM) front-end by the R²CDC results in 114 aFrms/0.37 Ωrms resolutions and a worst-case temperature-drift...

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is base...

A broadband process, voltage, and temperature (PVT)-insensitive noise-canceling balun-low-noise amplifier (LNA) was implemented in the 0.13- $\mu \text{m}$ CMOS process for subgigahertz wireless communication applications. The proposed LNA is based on the traditional common-gate common-source (CGCS) balun-LNA topology, and it adopts the diode-conn...

This article presents an ultra-low-noise differential relaxation oscillator that achieves a phase noise figure of merits (FoMs) of 157.7 and 162.1 dBc/Hz, respectively, at 1- and 100-kHz frequency offsets. The oscillator is inherently robust against 1/f noise, while swing-boosting minimizes the phase noise arising out of thermal noise. Furthermore,...

This paper presents an ultra-low-power receiver based on the injection-locked oscillator (ILO), which is compatible with multiple modulation schemes such as on-off keying (OOK), binary frequency-shift keying (BFSK), and differential binary phase-shift keying (DBPSK). The receiver has been fabricated in 0.18 μm CMOS technology and operates in the IS...

This paper presents an ultra-low power, low cost demodulator for gaussian frequency shift keying (GFSK) receivers that use low intermediate frequencies (IF). The demodulator employs a direct IF to digital data conversion scheme by using an injection-locked ring oscillator (ILRO) with a 1-bit flip-flop. It consumes 2.7 μW from a 1.0 V supply at a da...

This paper presents a fully differential implantable neural recording front-end IC for monitoring neural activities. Each analog front-end (AFE) consists of a low-noise amplifier (LNA), a variable gain amplifier (VGA), and a buffer. The output signal of the AFE is digitized through a successive approximation register analog-to-digital converter (SA...

In this paper, we propose a fully-differential amplitude-shift-keying (ASK) demodulator for suppressing the effect of undesired common mode variations on the received data, In addition, the ASK demodulator is robust against power supply ripples. The proposed demodulator consists of a fully-differential envelope detector (ED), programmable gain ampl...

A low-voltage, low-power, capacitance-to-digital converter (CDC) that is insensitive to supply and temperature variations is presented in this paper. The CDC comprises two matched RC oscillators and a counter-based programmable digital converter. The transfer function of the proposed CDC is a scaled ratio of the capacitors having equal drift coeffi...

Low-power CMOS reference clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as implantable biomedical devices and smart sensors [1-3]. In such SoCs, as the supply voltage shrinks and the level of analog and digital circuit integration increases to meet rigorous power and area constraints, the noise from othe...

Body channel communication (BCC) integrated circuits for emerging wireless body area network multimedia applications call for the need of high-speed inter-device data communication at ultra-low-power consumption and smaller device footprint. In this paper, a novel low-power injection-locking-based clock-recovery circuit (CRC) is proposed for BCC tr...

With the growing number of wearable devices and applications, there is an increasing need for a flexible body channel communication (BCC) system that supports both scalable data rate and low power operation. In this paper, a highly flexible frequency-selective digital transmission (FSDT) transmitter that supports both data scalability and low power...

Wearable technology is opening the door to future wellness and mobile experience. Following the first generation wearable devices in the form of headsets, shoes and fitness monitors, second generation devices such as smart glasses and watches are making an entrance to the market with a great potential to eventually replace the current mobile device...

This paper presents a trim-free low-voltage and low-power CMOS current reference which achieves high current stability to temperature variation. In order to achieve process-insensitive temperature compensation, the proposed circuit employs ratio between the process-independent temperature coefficients of resistor and compensation voltage. The propo...

A low-voltage, low-power CMOS voltage reference with high temperature stability in a wide temperature range is presented. The temperature dependence of mobility and oxide capacitance is removed by employing transistors in saturation and triode regions and the temperature dependence of threshold voltage is removed by exploiting the transistors in we...

A 10MHz, 80μW CMOS reference clock oscillator is presented in 0.18μm CMOS. The proposed oscillator employs a supply-regulated ring-oscillator in a temperature compensated feedback loop, which minimizes the frequency sensitivity to supply and temperature variations. The clock oscillator achieves frequency variation of less than ±0.05% against supply...

In this paper, an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented. To achieve low jitter, the clock generator uses an LC-VCO with S-bit switched tuning scheme. The clock output is taken from the output of a multi-modulus divider, which increases the output frequency range with small...