High Output Impedance Current-Mode Universal First-Order Filter With Three Inputs Using One DDCC

Abstract

Background
A current-mode universal first-order filter with three input terminals and one output terminal is presented.

Methods
The proposed circuit uses one differential difference current conveyor (DDCC), one grounded capacitor and two resistors.

Results
This circuit offers the following advantageous features: high output impedance, employing only one active component, using a grounded capacitor, the versatility to synthesize any type of first-order filter transfer functions.

Conclusion
Each standard first-order filter function can be obtained by using only one current input signal from the proposed circuit.

Full text

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Recent Advances in Electrical & Electronic Engineering, 2019, 12, 00-00 1
RESEARCH ARTICLE
2352-0965/19 $58.00+.00 © 2019 Bentham Science Publishers
High Output Impedance Current-Mode Universal First-Order Filter With
Three Inputs Using One DDCC
Jiun-Wei Horng*
Department of Electronic Engineering, Chung Yuan Christian University, Chung Li District, Taoyuan City, 32023,
Taiwan
Abstract: A current-mode universal first-order filter with three input terminals and one output terminal
is presented. The proposed circuit uses one differential difference current conveyor (DDCC), one
grounded capacitor and two resistors. This circuit offers the following advantageous features: high
output impedance, employing only one active component, using a grounded capacitor, the versatility to
synthesize any type of first-order filter transfer functions. Each standard first-order filter function can be
obtained by using only one current input signal from the proposed circuit.
A R T I C L E H I S T O R Y
Received: March 31, 2018
Revised: May 14, 2018
Accepted: May 17, 2018
DOI:
10.2174/2352096511666180525124701
Keywords: Active filter, current conveyor, current-mode, first-order, frequency response, universal filter.
1. INTRODUCTION
Current conveyor (CC) based active filters are of great
interest because their high signal bandwidths, greater
linearity and larger dynamic range [1]. In analog circuit
design, if current-mode active filters have the feature of high
output impedance, they can be directly connected in cascade
to implement higher order filters [2-4]. Moreover, if the
circuits use only grounded capacitors, they are beneficial
from the point of view of integrated circuit fabrications [5-
6].
Several current-mode first-order allpass filters using
various active components have been reported [7-18]. But
only allpass filter signals can be obtained from these circuits.
Several current-mode first-order filters using differential
voltage current conveyors (DVCCs) or current differencing
transconductance amplifiers (CDTAs) were reported [19-20].
But only highpass and lowpass first-order filter signals can
be obtained from these circuits.
A current-mode universal first-order filter with one input
terminal and three output terminals using two multi-output
second-generation current conveyors, one grounded
capacitor and one grounded resistor was presented [21].
However, the active elements it used are not minimum. A
current-mode universal first-order filter with two input
terminals and one output terminal was presented [22].
Because this circuit requires two current input signals for
realizing the highpass or allpass filters, the input current
signal must be duplicated and the other current follower is
needed in practical circuit applications. Because of this
current follower, the new parasitic zeros were introduced to
the transfer functions; this solution will degrade the
performance of this circuit [23-24].
*Address correspondence to this author at the Department of Electronic
Engineering, Chung Yuan Christian University, Chung Li District, Taoyuan
City, 32023, Taiwan; E-mails: jwhorng@cycu.edu.tw
A current-mode universal first-order filter that uses one
current difference buffered amplifier (CDBA), two resistors,
one capacitor and three switches with one input terminal and
two output terminals was presented [25]. However, the
output impedances of this circuit are low and employ
floating capacitor in the realization of allpass response.
In this paper, a current-mode universal first-order filter
with three input terminals and one output terminal is
presented. The proposed circuit uses one differential
difference current conveyor (DDCC), one grounded
capacitor and two resistors. The new circuit offers the
following advantageous features: the versatility to synthesize
any type of first-order filter transfer functions by using only
one current input signal, using a grounded capacitor and high
output impedance.
2. PROPOSED CIRCUIT
Using standard notation, the port relations of a DDCC
can be described by the following matrix equation [26]:



















































z
x
y
y
y
z
x
y
y
y
v
i
v
v
v
i
v
i
i
i
3
2
1
3
2
1
01000
00111
00000
00000
00000
(1)
where the plus and minus signs indicate whether the
DDCC is configured as a non-inverting or inverting circuit,
termed as DDCC+ or DDCC-.
The proposed current-mode three-inputs-one-output
universal first-order filter is shown in Fig. 1. This circuit
comprises one DDCC, one grounded capacitor and two
resistors. Circuit analysis yields the following output current:

2 Recent Advances in Electrical & Electronic Engineering, 2019, Vol. 12, No. 1 Jiun-Wei Horng
Fig. (1). The proposed DDCC based current-mode universal first-
order filter.
1 1 2 2 1 1 3
1
()
in in in
out
sCI G I sCR G G I
IsC G
  

(2)
From (2), we can see that four circuit types can be
obtained from Fig. 1:
(1) If Iin2 = Iin3 = 0 (opened); Iin1 = input current signal, a
highpass filter can be obtained at Iout;
(2) If Iin1 = Iin3 = 0 (opened); Iin2 = input current signal, a
lowpass filter can be obtained at Iout;
(3) If Iin1 = Iin2 = 0 (opened); R2 = R1, Iin3 = input current
signal, an allpass filter can be obtained at Iout;
(4) If Iin3 = 0 (opened); Iin1 = Iin2 = Iin = input current
signal, an allpass filter can be obtained at Iout.
Thus, the circuit is capable of realizing all first-order
filter functions. From the first three filter types, three kinds
of standard filter functions can be obtained by using only one
input terminal. The allpass filter function can be obtained at
type four without component matching condition. From Fig.
1, the Iout output terminal has the advantage of high output
impedance. If the output current terminal with higher output
impedance is required, the metaheuristics as described in
Ref. [27] may be used.
3. SENSITIVITIES ANALYSIS
Taking the non-idealities of the DDCC into account, the
relationship of the terminal voltages and currents of DDCC
can be rewritten as



















































z
x
y
y
y
k
z
x
y
y
y
v
i
v
v
v
s
sss
i
v
i
i
i
3
2
1
321
3
2
1
0)(000
00)()()(
00000
00000
00000


(3)
where
)(s
j

represents the frequency transfer function of
the internal voltage follower and
)(s
k

represents the
frequency transfer function of the internal current follower of
the DDCC. These non-ideal frequency transfer functions can
be approximated by first-order lowpass functions, which can
be considered to have a unity value for frequencies much
lower than their corner frequencies [28]. If the circuit is
working at frequencies much lower than the corner
frequencies of
)(s
j

and
)(s
k

, then
jvjj s

 1)(
and
jv

(
jv

<<1) denotes the voltage tracking error from yj
terminal to x terminal of the DDCC and
)(s
k

=
k

=
ki

1
and
ki

(
ki

<<1) denote the current tracking error of the
DDCC. The denominator of the non-ideal output current
function for Fig. 1 becomes
1 1 3 2 1
( ) ( )D s sC G
   
   
(4)
Fig. (2). The non-ideal DDCC model.
The cutoff frequency is obtained by
1 3 2 1
1
()
cCR
   



(5)
The active and passive sensitivities of
c

are calculated
as
11
,1
cc
CR
SS


  
;
1 3 2
,1
cc
SS

  
  
.
All the active and passive sensitivities are low.
4. INFLUENCES OF PARASITIC ELEMENTS
A non-ideal DDCC model is shown in Fig. 2 [29]. It is
shown that the real DDCC has parasitic resistors and
capacitors from y and z terminals to the ground, and also, a
series resistor at the input terminal x. Taking into account the
DDCC with parasitic elements and assuming the circuits are
working at frequencies much lower than the corner
frequencies of
)(s
j

and
)(s
k

, namely,
1 kj

.
Moreover, in practical circuit design, the external resistors
can be chosen to be much smaller than the parasitic resistors
at y and z terminals of DDCC and much greater than the
parasitic resistance at x terminal of DDCC, i.e. Ry, Rz >> Rk
>> Rx. The external capacitance C can be chosen to be much
greater than the parasitic capacitors at the y and z terminals

High Output Impedance Current-Mode Universal First-Order Filter Recent Advances in Electrical & Electronic Engineering, 2019, Vol. 12, No. 1 3
of the current conveyor, i.e. Cy, Cz << C. The output current
of Fig. 1 becomes
22 2 2 2 1
2 1 1 2 2 1 1 2 3
22 2 1 2
[ ' ' ( )]
(2 ) ( ' )
''
y y a in
y in in
out
y
s C C sC G G G G I
sC G G G I sC G G G I
Is C C sC G G G
  
   

(6)
where
131
'zyy CCCCC 
,
131 zyya GGGG 
.
In equation (6), the undesirable factors are yielded by the
non-idealities of the DDCC. The conductances Ga and Gy2
become non-negligible at very low frequencies. The effects
of capacitance Cy2 become non-negligible at very high
frequencies. To minimize the effects of the DDCC’s non-
idealities, the operation angular frequency should be
restricted to the following condition:


2
'
ya
GG
C

(7)


min{
12
12
'y
GG
CC
,
2
2
2y
G
C
} (8)
5. SIMULATION RESULTS
The proposed current-mode universal first-order circuit in
Fig. 1 was simulated by HSPICE with 0.18

m, level 49
parameters from TSMC for verification. The CMOS
implementation of DDCC is shown in Fig. 3 [28]. The aspect
ratios of NMOS and PMOS transistors are W/L=4.5u/0.9u
and W/L=9u/0.9u, respectively. The power supply was

0.9V. The bias voltages are Vb = -0.38V.
Fig. 4 represents the simulated frequency responses for
the highpass filter of Fig. 1 with Iin2 = Iin3 = 0 (opened); Iin1 =
input current signal. Fig. 5 represents the simulated
frequency responses for the lowpass filter of Fig. 1 with Iin1
= Iin3 = 0 (opened); Iin2 = input current signal. Fig. 6
represents the simulated frequency responses for the allpass
filter of Fig. 1 with Iin1 = Iin2 = 0 (opened); Iin3 = input current
signal. The passive components are set to be C = 10pF and
R1 = R2 = 10k

with fc = 1.59155 MHz.
Fig. (4). Simulated highpass filter frequency responses of Fig. 1
design with C = 10 pF, R1 = R2 = 10 k

, Iin1 is the input signal.
Fig. (5). Simulated lowpass filter frequency responses of Fig. 1
design with C = 10 pF, R1 = R2 = 10 k

, Iin2 is the input signal.
Fig. (3). The CMOS realization of DDCC.

4 Recent Advances in Electrical & Electronic Engineering, 2019, Vol. 12, No. 1 Jiun-Wei Horng
Fig. (6). Simulated allpass filter frequency responses of Fig. 1
design with C = 10 pF, R1 = R2 = 10k

, Iin3 is the input signal.
Fig. (7). THD analysis results of the proposed current-mode allpass
filter.
Fig. (8). Time-domain input (upper signal) and output signal
waveforms demonstrate the ac dynamic range of the proposed
allpass filters;
In Fig. 7, total harmonic distortion (THD) of the current
allpass signals (Iin1 = Iin2 = 0; Iin3 = input current signal) is
given at 1.59155 MHz operation frequency designed with: C
= 10pF and R1 = R2 = 10k

. Fig. 8 shows the input and
output signals of the proposed filter designed with Iin1 = Iin2 =
0; Iin3 = input current signal at 1.59155 MHz operation
frequency, C = 10pF, and R1 = R2 = 10k

. It is observed
that 14µAp-p input current signal levels are possible without
significant distortion.
CONCLUSION
A new current-mode first-order universal filter circuit
using one DDCC, one grounded capacitor and two resistors
with three input terminals and one output terminal is
presented. The proposed circuit has the advantages of high
output impedance and uses a grounded capacitor. Moreover,
the proposed circuit can synthesize any type of first-order
active filter transfer functions by using only one current
input signal. The simulation results have been performed for
the proposed first-order three-inputs-one-output universal
filter to verify the theoretical expectation.
ETHICS APPROVAL AND CONSENT TO
PARTICIPATE
Not applicable.
HUMAN AND ANIMAL RIGHTS
No Animals/Humans were used for studies that are base
of this research.
CONSENT FOR PUBLICATION
Not applicable.
CONFLICT OF INTEREST
The authors declare no conflict of interest, financial or
otherwise.
ACKNOWLEDGMENTS
Declared None.
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