Jiajun Luo

Chinese Academy of Sciences | CAS · Silicon Device and Integration Technology Department

Silicon-on-insulator (SOI) devices are widely utilized in high-performance and high-reliability fields, facing challenges from self-heating effects (SHE). However, the research on heat dissipation path closely related to SHE remains incomplete. This paper initiates an in-depth analysis of thermal effects involving the fine structures within heat di...

The development of brain-inspired spiking neural networks (SNNs) has great potential for neuromorphic edge computing applications, while challenges remain in optimizing power-efficiency and silicon utilization. Neurons, synapses and spike-based learning algorithms form the fundamental information processing mechanism of SNNs. In an effort to achiev...

In this paper, the dynamic self-heating effect (SHE) of silicon-on-insulator (SOI) MOSFETs is comprehensively evaluated by ultrafast pulsed I – V measurement. For the first time, it’s found that the complete heating response and cooling response of SHE for SOI MOSFETs are conjugated two-stage curves. We establish the effective thermal transient res...

The electrical performance of high-precision analog and digital circuits in MOSFETs is highly sensitive to temperature changes. Here, by studying the stability of electrical characteristics such as OFF-state leakage current, saturation current, and transconductance efficiency of fully depleted silicon-on-insulator (FDSOI) and partially depleted sil...

Recent years have seen an increasing popularity in the development of brain-inspired neuromorphic hardware for neural computing systems. However, implementing very large scale simulations of neural networks in hardware is still an open challenge in terms of power efficiency, compactness, and biophysical resemblance. In an effort to design biologica...

The ongoing trend towards miniaturization and increased packaging density has exacerbated the reliability problem of Au-Al heterogeneous metal bonding structures in high-temperature environments, where extreme temperatures and high current pose a serious challenge. In order to address this issue, the present study aims to investigate the electromig...

In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at...

Partially-depleted silicon-on-insulator (PDSOI) MOSFETs with full dielectric isolation structure are widely used in the high temperature field of 225 ℃, but affected by the threshold voltage and carrier mobility, the saturated output current has a rate of change as high as 24.9% at 25~300 ℃, which will reduce the working speed and accuracy of the a...

The self-heating effect (SHE) of silicon-on-insulator (SOI) MOSFETs brings challenges to the measurement and modeling of transient electrothermal characteristics. For the first time, this study obtains the transient two-stage thermal equivalent RC network of SOI MOSFETs by nano double-pulse measurement combined with network identification by a de...

A mixed-signal spiking neural network (SNN) chip is presented, and its radiation effect-Total Ionizing Dose (TID) was studied. The chip was fabricated in a 180 nm silicon-on-insulator (SOI) integration process with an area of 3.75 mm2; the total doses were set at 300 krad (Si), 500 krad (Si), and 1 Mrad (Si). The TID radiation experimental results...

PDSOI is widely used in 225°C high-temperature electronic system applications with integrated circuits. But the process node stays at 0.5 um for a long time and no further breakthrough can be achieved. This paper reports the high-temperature characteristics of 28 nm ultra-thin-body FDSOI with LVT (Low threshold Voltage) structure. Experimental resu...

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The synergetic effects of total ionization dose and high-temperature stress of silicon on insulator (SOI) FinFETs (FF) are investigated under ON-state bias condition. The experiments and TCAD simulations are employed to analyze the influence of different trapped-charges in the gate and buried oxide on the threshold voltage and mobility variations o...

A layout technique to mitigate single-event transient (SET) is presented for monolithic 3D (M3D) integrated circuit through TCAD simulation. The effect of transistor- and gate-levels M3D on SET is investigated from the generation and propagation stages. The resulting SET characteristics show that transistor-level M3D exhibits stronger pulse quenchi...

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM...

Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 °C to 195 °C are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated witha 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted...

As a promising candidate in space radiation hardened applications, silicon-on-insulator (SOI) devices face the severe problem of total ionizing dose (TID) radiation because of the thick buried oxide (BOX) layer. The direct-current current–voltage (DCIV) method was applied for studying TID radiation of SOI metal–oxide–semiconductor field–effect tran...

The impact of back-gate on the single event upset (SEU) for monolithic 3-D (M3D) 6T SRAM was investigated. Compared with planar SRAM, M3D SRAM exhibits higher SEU sensitivity and a different bias effect. It is found that applying negative and positive back-gate bias respectively to NMOS and PMOS helps to reduce the SEU sensitivity for M3D SRAM. The...

The effects of proton irradiation on the electrical and optical properties of hybrid perovskite photodetectors have been investigated in this paper. Our results reveal that no significant changes in the photoelectric properties of the perovskite photodetectors are observed when the proton fluence accumulates to 1×1012 p/cm2. However, with further i...

The single event upset (SEU) for monolithic 3-D (M3D) 6T SRAM with different channel sizes was investigated based on a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology over a temperature range from 210 K to 390 K. Compared with planar SRAM, M3D SRAM exhibits higher SEU sensitivity and increasing the transistor size does not work in mit...

This paper studies the effects of process node and circuit schemes on the electromagnetic susceptibility (EMS) of current reference circuits. Three reference circuits using PDSOI with technology node of 0.5 μm (VREF50), 0.35 μm (VREF33) and 0.18 μm (VREF18) are used. VREF50 has an additional CASCODE structure to achieve a PSRR enhancement. The test...

Correlated double sampling (CDS) circuits are essential to processing the X-ray charge-coupled devices (CCDs) that have been widely used in the modern X-ray astronomical field. For timing observations, both energy resolution and timing resolution are of great importance. We are developing the XCR4C application-specific integrated circuit (ASIC), wh...

The effects of the white-light X-ray and 170-keV proton beam irradiation on the electrical and optical characteristics of the InGaN/GaN multiple quantum wells (MQWs) light-emitting diodes (LEDs) are analyzed and compared. Different from the negative effects of the proton irradiation, the X-ray irradiation shows positive effects on the LEDs’ perform...

In this paper, a transient ionizing radiation SPICE model for PDSOI MOSFET is proposed for the simulation of the rail‐span collapse. It is based on the present understanding of transient ionizing radiation effects. The model accounts for the generation and collection of radiation induced transient photocurrent, the influence of the device geometry,...

Influences of 170-keV protons beam irradiation on the static and dynamic properties of blue light InGaN/GaN multiple quantum wells (MQWs) microlight-emitting diodes (MicroLEDs) were investigated. It was interesting to find out that, although threshold voltage and light output power of Micro-LEDs deteriorated after proton irradiation, a 3-dB bandwid...

An analysis model of snapback voltage for the base resistance controlled thyristor (BRT) is developed in this paper. It's shown that, improving hole current flowing into P-base region is an important way to suppress snapback phenomenon during forward conducting state. Thus, a new BRT with a floating N-region in N-drift layer is proposed. In this ne...

This paper proposes a probabilistic analysis technique to evaluate the single event transient sensitivity. Using the technique in both the time domain and spatial domain, Single-Event Transients (SET) sensitivity of a Phase-Locked-Loop (PLL) designed for SET mitigation has been analyzed as an example. Statistical results of simulation can figure ou...

Fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs fabricated in 0.2 μm SOI technology with external body contact (EBC) and floating body (FB) structures are irradiated up to 500 krad(Si) using 60Co gamma rays under the transmission gate (TG) and OFF bias conditions, respectively. The threshold voltage shift of the back transistors due to radi...

This paper investigates the effect of total ionizing dose radiation on back-gate interface traps in SOI NMOSFETs. The concentration and energy distribution of interface traps at Si/SiO2 back-gate interface of SOI NMOSFETs during irradiation are studied by the direct-current current-voltage technique. When transistors are subjected to radiation, DCI...

A base resistance controlled thyristor with semi-superjunction (Semi-SJ BRT) is proposed in this paper. The highly doped P-pillar in drift region extracts injected holes into thyristor, then hole current density in thyristor will be improved and parasitic transistor is significantly suppressed. Meanwhile, highly doped drift region reduces drift res...

Radiation effects of 10 MeV electrons on blue-lighting InGaN/GaN multiple quantum wells (MQWs) and ultraviolet-lighting GaN/AlGaN MQWs were investigated and compared by means of temperature-dependent and time-resolved photoluminescence (PL) methods. It was found that GaN/AlGaN MQWs showed better radiation tolerance than InGaN/GaN MQWs. In detail, t...

The failure mechanism of vertical double-diffusion metal-oxide-semiconductor (VDMOS) turning on under capacitive loads is analyzed. Due to the structural features of the device, it is easy to burnout at the source pad (SPAD) area when turning on under capacitive loads. On the basis of simulation, thermal characteristics of VDMOS devices under capac...

High-resolution X-ray diffraction, temperature-dependent photoluminescence (PL), time-resolved PL and positron annihilation spectroscopy are employed to investigate the degradation mechanism of InGaN/GaN multiple quantum wells (MQWs) light emitting diodes (LEDs) under silicon ion irradiation. Reduction of the quantum-confined Stark effect due to cr...

In our work, insights into the total dose response and native point defect behavior in the Al2O3 gate dielectric during irradiation were gained by gamma-ray irradiation experiments and first-principles calculations. It is found that the O vacancy (VO) can act as a hole trap in the Al2O3 gate dielectric during irradiation, leading to the negative sh...

The changes of interface trap density and distribution at the Si/SiO2 interface in partially depleted SOI MOSFETs were investigated by direct-current current–voltage (DCIV) method before and after Fowler–Nordheim tunnelling stress condition. The equivalent density and energy level of interface trap were obtained by combining the DCIV measurement re...

The total ionizing dose response of bulk nFinFETs with multiple gate lengths and multiple fins is investigated for on-state bias condition. Experiments and TCAD simulations were performed to analyze the effect of the trapped charges in the gate oxide and shallow trench isolation (STI) oxide on the threshold voltage and transconductance of the devic...

The existence of buried oxide layer and the strong coupling effect between the front and back channels can worsen the radiation-induced degradation on fully-depleted SOI (FDSOI) device. To mitigate the radiation impact, a new structure named Double-SOI (DSOI) is introduced in this paper. This new structure exhibits potential benefits of reducing th...

The flexibility and diversity of organic chemistry have yielded many materials in which magnetism can be varied. However, most methods used for changing magnetism are inefficient or destructive to the magnetic material. Here we report high-performance magnetic control of a gas-responsive single-molecule magnet (SMM). The results exhibit that the ma...

We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive r...

The 1-Mb and 4-Mb commercial toggle magnetoresistive random-access memories (MRAMs) with and 0.18- complementary metal–oxide–semiconductor (CMOS) process respectively and different magnetic tunneling junctions (MTJs) are irradiated with a Cobalt-60 gamma source. The electrical functions of devices during the irradiation and the room temperature ann...

In this study, we investigate the single-event transient (SET) characteristics of a partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor (MOS) device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET se...

Correlated double sampling (CDS) circuits are essential to process the X-ray charge-coupled devices (CCDs) that have been used in the modern X-ray astronomical field. A novel CDS circuit is presented. The innovation of the circuit is that it greatly improves the noise and linearity performances through moving the clamping switch out of the signal p...

We present a detailed study of a superjunction (SJ) nanoscale partially narrow mesa (PNM) insulated gate bipolar transistor (IGBT) structure. This structure is created by combining the nanoscale PNM structure and the SJ structure together. It demonstrates an ultra-low saturation voltage (V ce(sat)) and low turn-off loss (E off) while maintaining ot...

This work presents the development of a four-channel correlated double sampling (CDS) ASIC, named CD-S4C, targeting the readout of a type of multi-readout swept charge device (SCD) for applications in the fields of both X-ray spectroscopy and imaging. Compared with conventional CDS architecture based on clamping technique, the innovation of the CDS...

Failure analysis is carried out in an irregular way because failure occurred in different situations with different phenomena. Experiences are usually needed to do failure analysis. When a new failure case occurs, it is difficult to make an effective scheme to implement the failure analysis without experiences. To solve this problem, an analysis me...

A double silicon on insulator (DSOI) structure was introduced based on fully depleted SOI (FDSOI) technology. The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices. Based on DSOI ring oscillator (OSC), this paper focused on the theoretical analysis and electrical t...

The experimental results of the cryogenic temperature characteristics on 0.18-μm silicon-on-insulator (SOI) metal-oxide-silicon (MOS) field-effect-transistors (FETs) were presented in detail. The current and capacitance characteristics for different operating conditions ranging from 300 K to 10 K were discussed. SOI MOSFETs at cryogenic temperature...

With the improvement of packaging technology, small packaging type is gradually becoming mainstream. Packaging dimension has a significant influence on the performance and reliability of power Vertical Double diffused MOSFET (VDMOS) device. In this paper, the thermal stress of different shell-tube dimensions in power VDMOS device is simulated by fi...

Extra charge will be generated and deposited into the cell when an energetic ion strikes the SOI SRAM. The sensitive regions will collect the deposited charge. This may upset the logic values stored in SRAM. The Geant4 is a very useful tool to simulate the process above. The GDML (Geometry Description Markup Language) file can be used to model the...

Single event transient (SET) issues become a primary concern in modern CMOS logic circuits. The possibility of soft errors due to the propagation of SETs is increasing, and becomes a significant reliability challenge. In this paper, single event transients in a 100 series 0.18 μm partially-depleted Silicon-On-Insulator (PDSOI) CMOS inverter chain a...

A novel integrated digital controller for buck converter based on the direct system-variable calculation is presented. Compared with linear compensators, the discrete-time direct controller is conceived to generate an additional control variable during each switching period that increases the convergence rate when system states change. An all-digit...

A premature failure has been investigated and proved to be caused by the sparkover between no-connect metal cover and chip of ceramic packaging. Sparkover-induced model with the parasitic parameters of human body and ESD(electrostatic discharge) tester was created to explain the failure mechanism. Simulation and experiment were performed to verify...

3D fully-depleted silicon-on-insulator (FDSOI) n-channel transistor model is constructed by the accurate calibration between process information from OKI and Synopsys TCAD tool. Single-event-effect (SEE) simulations are conducted based on the 3D model to evaluate the collected charge from different heavy ion strike locations. The channel is the mos...

The shallow source and drain is used in the PDSOI technology. Unfortunately, most of the standard commercial SOI MOSFET model is for the device with deep source and drain, the necessity of the new models for this device arises. A simulation model is proposed based on the 0.13μm PDSOI process developed by the Institute of Microelectronics of the Chi...

The STI stress effect is investigated based on the 0.13 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). It shows that the threshold voltage and mobility are all affected by the STI stress. The absolute value of the threshold voltage of NMOS and PMOS increased by about 10%, the saturation cu...

This paper investigates the influence of metal spacing and poly-crystalline silicon gate and silicide technology on single event transients (SETs) occurring in pulsed laser irradiated test patterns based on 0.18 μm partially depleted silicon-on-insulator complementary-metal-oxide-semiconductor technology. Laser-induced transients were measured and...

The human body model (HBM) stress of a no-connect metal cover is tested to obtain the characteristics of abnormal electrostatic discharge, including current waveforms and peak current under varied stress voltage and device failure voltage. A new discharge model called the "sparkover-induced model" is proposed based on the results. Then, failure mec...

The shallow trench isolation (STI) y-stress effect on deep submicron PDSOI MOSFETs was studied. Instance parameters SAy, SBy and model parameters a1, a2, b1, b2 were proposed to build a compact model for this effect. This model can be easily implemented in the SOI MOSFET compact model like BSIMSOI model. By using this model, we can simulate the STI...

This paper describes an improved driving circuit scheme including a slew-rate enhancement circuit for organic light-emitting-diode-on-silicon (OLEDoS) microdisplay design. Due to the basic pixel cell area of OLEDoS microdisplay being less than 300 μm2, pixel currents are always needed to modulate from hundreds of pico-amperes (pA) to tens of nano-a...

This paper presents a new phenomenon, where the holding-voltage of a silicon-controlled rectifier acts as an electrostatic-discharge protection drift in diverse film thicknesses in silicon-on-insulator (SOI) technology. The phenomenon was demonstrated through fabricated chips in 0.18 μm SOI technology. The drift of the holding voltage was then simu...

An 800 × 600 pixel organic light-emitting diode-on-silicon (OLEDoS) driving circuit is proposed. The pixel cell circuit utilizes a subthreshold-voltage-scaling structure which can modulate the pixel current between 170 pA and 11.4 nA. In order to keep the voltage of the column bus at a relatively high level, the sample-and-hold circuits adopt a pin...

An ion vertical striking on SOI CMOS transistor sensitive region creates an obvious large current resulting in upset of output node. Since parasitic BJT act, the single-event effect (SEE) is enhanced. In order to evaluate this effects, it is desirable to calculate critical charge (Qcrit, charge collected by the drain during the entire SEE) and the...

A new Bootstrapped Charge-Recovery Logic (BCRL) driven by two-phase non-overlap power clock is presented. The logic value of BCRL circuit is calculated by the CMOS-latch type circuits, and the loads are driven full-adiabatically by bootstrapped NMOS transistors with full-swing operation. Comparison between the powers of static CMOS and state-of-art...