Jeevan Battini

Kakatiya Institute of Technology and Science | KITS · Department of Electronics and Communication Engineering

Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using...

This paper proposes a novel architecture of novel excess-1 adder based Carry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed 4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates such as XOR gates are completely eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA is...

The design of a 20-FinFET novel full adder (NFA) with a new architecture employing Double Gate-FinFETs is presented in this work. The feature of new topology is, the input carry of full adder has to traverse through single transistor, by which the speed of full adder is enhanced. Carry propagation is a critical factor in determining the speed of mu...

This paper presents a FinFET based Single Circuit (FSC) used to realize Active-High output Decoder (AHD), Active-Low output Decoder (ALD), and Digital Multiplexer. The input signal is traversed through a single transmission gate irrespective of the size of FSC is the uniqueness of the proposed multiplexer. The new architectures of FSC use an equal...

Conventional CMOS has become successful logic for most digital VLSI circuits and a good candidate in terms of power dissipation. But due to its dual nature, more transistors are required and are not suitable as the technology is scaled down. This paper proposes a Double Gate (DG) FinFET based 4-1, 8-1, 16-1 multiplexer (DFMs) with a reduced number...

A novel non-CMOS 4-1 multiplexer using heterogeneous logic style is presented in this brief. The heterogeneous logic design uses the combination of three basic logic styles such as Dual Value Logic (DVL), Transmission Gate Logic (TGL) and Simple Pass Transistor Logic (SPTL). The design uses only two stacking transistors in between the supply rails....

This paper presents a new high-speed approximate multiplier using compressor and carry-look-ahead (CLA) adder to increase the speed of the computations. The number of full adders is reduced by introducing compressors. The CLA adder will reduce the waiting time by generating all carry at single instant. Initially, a 4 × 4 multiplier is designed usin...

This paper presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry Save Multiplier. The design achieves high speed with maximum frequency of 526 MHz compared to existing floating point multipliers. The floating point multiplier is dev...