Guido Groeseneken

imec · Process Technology

Voltage control of the magnetic anisotropy (VCMA) effect enables a voltage-mediated magnetization switching mechanism for lower-power applications. In this work, we experimentally investigate the characteristics of VCMA-induced switching and we observe a clear decrease in the critical switching voltage (Vc) at elevated temperatures. A 50% reduction...

We propose a deterministic VCMA writing concept that allows exclusion of the pre-read which is required in conventional VCMA write scheme. We apply it on 400°C compatible pMTJ devices with high TMR 246% and retention Δ = 54 and demonstrate a genuine ns-scale write speed. Furthermore, we realize reliable 1.1GHz external field-free VCMA switching wit...

The observation of a significant temperaturedependent variation in the I-V characteristics of tunneling devices is often interpreted as a signature of a trapassisted-tunneling dominated current. In this letter, we use a ballistic 2D quantum-mechanical simulator, calibrated using the measured temperature-dependent I-V characteristics of Esaki diodes...

Co-integration of the key power stage, namely gate drivers and half-bridge in a single-die solution, is a tremendous and inevitable challenge to realizing GaN power integrated circuits (GaN power ICs). In this letter, a monolithically integrated GaN half-bridge including the drivers were successfully fabricated on 200-mm engineered substrates of Qr...

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used...

We investigate bias temperature instability (BTI) charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals (WFMs). Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work...

Junction-less FETs are used as top-tier device in a 3D sequential integration. Due to the low thermal budget allowed in the 3D integration, conventional inversion mode FETs show extremely poor BTI reliability. In contrast, junction-less FET shows improved BTI reliability, which is attributed to the reduced oxide electric field of operation. We obse...

In tunnel field-effect transistors, trap-assisted tunneling (TAT) is one of the probable causes for degraded subthreshold swing. The accurate quantum-mechanical (QM) assessment of TAT currents also requires a QM treatment of phonon-assisted tunneling (PAT) currents. Therefore, we present a multi-band PAT current formalism within the framework of th...

In the quantum mechanical simulation of exploratory semiconductor devices, continuum methods based on a k ⋅p/envelope function model have the potential to significantly reduce the computational burden compared to prevalent atomistic methods. However, full-zone k ⋅p/envelope function simulation approaches are scarce and existing implementations are...

A comprehensive study on buffer vertical leakage mechanism and buffer reliability of 200-mm GaN-on-SOI is conducted in this paper. The buffer vertical leakage current versus bias is found to sequentially comprise three ranges of low-field leakage, variable-range hopping, and breakdown. The low-field leakage increase at high temperatures has been pr...

Analogous device parameters in both the parallel (P) and anti-parallel (AP) states ensure a symmetric spin-transfer-torque magnetic random-access memory operation scheme. In this study, however, we observe an increasing asymmetry in the performance metrics with operating temperature of the bottom-pinned perpendicular magnetic tunnel junction (p-MTJ...

Operating temperature has a significant impact on the reliability of metal-oxide-semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects (ΔN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) at operating condition typically shows...

Discrepancies exist between the theoretically predicted and experimentally measured performance of band-to-band tunneling devices, such as Esaki diodes and tunnel field-effect transistors (TFETs). We resolve this discrepancy for highly-doped, direct-bandgap Esaki diodes by successfully calibrating a semi-classical model for high-doping-induced ball...

Dopant pockets in combination with a III-V heterostructure have become a staple in simulations of tunnel field-effect transistors (TFET) to achieve acceptable on-currents (ION) and to break the ION-subthreshold swing (SS) trade-off in pTFETs. Questions on the scalability and variability of these dopant pockets remain, however. We therefore propose...

Graphene interconnects are being considered as a promising candidate for beyond CMOS applications, thanks to the intrinsic higher carrier mobility, lower aspect ratio and better reliability with respect to conventional Cu damascene interconnects. However, similarly to Cu, line edge roughness can seriously affect graphene resistance, something which...

The backgating effect on trench-isolated enhancement- mode p-GaN devices fabricated on 200 mm GaN-on-SOI was investigated. We show that, to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully-isolated Si(111) device layers to keep...

STT-MRAM is a promising non-volatile memory for high speed applications. The thermal stability factor (Δ = Eb/kT) is a measure for the information retention time, and an accurate determination of the thermal stability is crucial. Recent studies show that a significant error is made using the conventional methods for Δ extraction. We investigate the...

2-D transition metal dichalcogenides (TMDs) are promising materials for CMOS application due to their ultrathin channel with excellent electrostatic control. TMDs are especially well suited for tunneling field-effect transistors (TFETs) due to their low-dielectric constant and their promise of atomically sharp and self-passivated interfaces. Here,...

To get a better insight into the vertical leakage mechanism of GaN-on-Si, the carrier transport from n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> , n, p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> , and p-Si(111) substrates through...

Since the first graphene layer was fabricated in the early 2000's, graphene properties have been studied extensively both experimentally and theoretically. However, when comparing the many resistivity models reported in literature, several discrepancies can be found, as well as a number of inconsistencies between formulas. In this paper, we revise...

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device's lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for character...

Ferroelectric (FE) hafnium oxide is a promising candidate for memory applications. In this paper, endurance, imprint, and retention tests are carried out on FE aluminum-doped hafnium oxide thin films with different electrodes: 1) metal-insulator-metal (MIM) and 2) silicon-insulator-silicon (SIS). MIM devices exhibit higher endurance than SIS device...

Extended transistor scaling has brought us a lot of benefits, but also a myriad of problems, including severe reliability issues [1] . To extend the scaling path as far as possible, system architects and technologists have to work together. They have to find solutions—e.g., at system level—to realize self-healing chips, chips that can detect or “f...

In this work, we have reported dual-gate amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs), where a top-gate self-aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a-IGZO TFTs under different gate control are compared. With the enhanced control of...

Ferroelectric hafnium oxide is a promising candidate for logic and memory applications as it maintains excellent ferroelectric properties at nm-size ensuring compatibility with state of the art semiconductor manufacturing. Most of the published papers report on the study of this material through Metal-Insulator-Metal capacitors or Metal-Insulator-S...

Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this paper, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epita...

Perpendicular magnetic anisotropy (PMA) is an essential condition for CoFe thin films used in magnetic random access memories. Until recently, interfacial PMA was mainly known to occur in materials stacks with MgO\CoFe(B) interfaces or using an adjacent crystalline heavy metal film. Here, PMA is reported in a CoFeB\Ta bilayer deposited on amorphous...

To predict the negative bias temperature instability (NBTI) toward the end of pMOSFETs' ten years lifetime, power-law-based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. n reported by early work spreads in a wide range and varies with measurement conditions, which ca...

In this work, we investigate the time-dependent breakdown mechanisms in edge terminated AlGaN/GaN lateral Schottky diodes under high temperature reverse bias (HTRB) tests. Thanks to a combined experimental/simulation analysis, we ascribe the device failure to two distinct time-sequential breakdown mechanisms caused by a localized electric field pea...

It is essential to understand the local potential distribution of solid-state nanopores in nanofluidic systems. However, applying gate voltage or adding external electrical probes tends to disturb the electric field and/or flow patterns. To solve this problem, an approach is described to monitor the local potential using electrochemical surface enh...

Two specialists in the field explain how to make self-healing chips.

The trap-assisted tunneling (TAT) current in tunnel field-effect transistors (TFETs) is one of the crucial factors degrading the sub-60 mV/dec sub-threshold swing. To correctly predict the TAT currents, an accurate description of the trap is required. Since electric fields in TFETs typically reach beyond 10(6) V/cm, there is a need to quantify the...

Non-filamentary RRAM is a promising technology that features self-rectifying, forming/compliance-free, tight resistance distributions at both high and low resistance states (HRS/LRS). Direct experimental evidence for its physical switching & failure mechanisms, however, is still missing, due to the lack of suitable characterization techniques. In t...

A Gate-All-Around (GAA) nanowire (NW) device is a candidate for sub-10nm bulk Si CMOS. The impact of the new architecture and its process options on intrinsic ESD performance needs to be studied. The measurement results and TCAD simulations prove that the ESD performance in bulk GAA NW based diodes is maintained in comparison to bulk FinFET diodes.

Physical mechanisms governing dielectric breakdown in planar devices have been well studied in the past [1, 2]. However, their extension to the study of non-planar FinFET structures has not received much attention, partly due to the assumption that the kinetics of failure would remain the same. We reveal in this study that this assumption is not tr...

The self-heating (SH) effect is studied experimentally and through simulations on an extensive set of industry-relevant solutions for FF and GAA-NW Si and high-mobility devices, with multiple processing options. Considerations for managing SH in future technologies are provided.

A new model for assessing NBTI and PBTI induced time-dependent variability under practical operation workloads is proposed. The model is based on a realistic understanding of different types of defects and has excellent predictive capability, as validated by comparison with experimental data. In addition, a new fast wafer-level test scheme for para...

In this paper, we have studied the impact on lateral Nanowire Transistor’s (LNW) performance of reducing the wire diameter from 7nm to 5nm. As technology scaling continues, the LNW device size is scaled here for beyond 7nm nodes. Reducing the NW’s gate length causes huge degradation in electrostatic control of the device. The degraded electrostatic...

Scaling of metal-oxide-semiconductor field-effect transistors (MOSFET) is hitting fundamental limits due to power issues. In this article, an alternative transistor concept, the tunnel FET (TFET), is discussed, which employs quantum mechanical band-to-band tunneling to reduce power consumption. The main operating principle is explained, followed by...

Perpendicular Magnetic Anisotropy (PMA) is a key requirement for state of the art Magnetic Random Access Memories (MRAM). Currently, PMA has been widely reported in standard Magnetic Tunnel Junction material stacks using MgO as a dielectric. In this contribution, we present the first report of PMA at the interface with a high-κ dielectric grown by...

In this letter, we propose a novel single-cell, cycle-to-cycle based retention testing method, enabling fast statistical retention assessment on oxide-based resistive random access memory (RRAM). Detailed comparison between cycle-to-cycle and device-to-device retention testing methods is made on TiN\HfO2\Hf stack showing excellent agreement in term...

Bulk FinFET is the main technology option for sub-20-nm CMOS nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant deterioration of intrinsic electrostatic discharge (ESD) performance. In this paper, the impact on ESD performance induced by the process options beyond 20-nm nodes is explored...

In this paper, we have extensively investigated the impact of anode recess on the reverse leakage current, forward voltage (V F), and dynamic characteristics of Au-free AlGaN/GaN Schottky barrier diodes with a gated edge termination (GET-SBDs) on 200-mm silicon substrates. By increasing the number of atomic layer etching (ALE) cycles for anode rece...

As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-call...

The impact of AlGaN barrier recess on the leakage, forward voltage, and dynamic characteristics of Al-GaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been investigated. With 4-nm remaining AlGaN barrier in the recessed anode region, GET-SBDs show a median leakage current of 1 nA/mm and a forward voltage of 1.26 V. We foun...

We present distinct asymmetric plasmon-induced noise properties of ionic transport observed through gold coated nanopores. We thoroughly investigated the effects of bias voltage and laser illumination. We show that the potential drop across top-coated silicon nanocavity pores can give rise to a large noise asymmetry (∼2-3 orders of magnitude). Vary...

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low- $k$ damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technolog...

We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and...

We investigate the DC and dynamic characteristics of AlGaN/GaN Schottky barrier diodes (SBDs) and the diodes with a gated edge termination (GET-SBD) fabricated on unintentional doped (UID) and carbon-doped AlGaN buffers. The off-state characteristics of diodes fabricated on UID buffer are dominated by buffer leakage and buffer breakdown voltage (BV...

In this paper we engineer a TiN Al2O3 (Hf,Al)O2 Ta2O5 Hf Oxide Resistive Random Access Memory (OxRRAM) device for fast switching at low operation current without sacrificing the retention and endurance properties. The integrated 40 nm × 40 nm cell switches at 10 μA using write pulses shorter than 100 ns (resp. 1 μs) for Reset (resp. Set) and with a...

In this paper, positive bias temperature instability (PBTI) in fully recessed gate GaN MIS-FETs is studied by using an eMSM (extended Measure-Stress-Measure) technique, which consists of a set of stress/recovery tests. By using this technique, VTH shift after a stress and the relaxation information can be collected in one experiment. First of all,...

We modeled the electrostatic doping in multilayer graphene interconnects by self consistently solving Poisson’s equation and we computed the resistivity per layer by accounting for acoustic and optical phonon scattering. For the analysis, we used two different doping concentrations, representative for graphene on top of hexagonal Boron Nitride and...

We explain in detail how to optimize the oxygen chemical potential profile of Ta2O5-based stack to improve switching speed at reduced operating current (<10μA). Using industry-relevant programming scheme, we demonstrate an oxide-based RRAM stack giving large on/off ratio (∼x200) while the good reliability properties are preserved.

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al₂O₃ gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxati...

In this letter, we identified a dominant buffer trapping causing a bias-dependent dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> for AlGaN/GaN Schottky barrier diodes (SBDs) fabricated on a C-doped AlGaN buffer as back-barrier. Current transient measurements at various temperatures...

Strain can strongly impact the performance of III-V tunnel field-effect transistors (TFETs). However, previous studies on homostructure TFETs have found an increase in ON-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-i-n TFETs submitted to uniax...

In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of ON-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver ~4 A at 2 V a...

We validate a model which is a combination of multiple trapping and release and percolation model for describing the conduction mechanism in amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT). We show that using just multiple trapping and release or percolation model is insufficient to explain TFT behavior as a function of tem...

As CMOS scales down, hot carrier aging (HCA) scales up and can be a limiting aging process again. This has motivated re-visiting HCA, but recent works have focused on accelerated HCA by raising stress biases and there is little information on HCA under use-biases. Early works proposed that HCA mechanism under high and low biases are different, ques...

We report a dual-gate (DG) self-aligned (SA) a-IGZO TFT process that comprises only five mask steps. The topgate (TG) is self-aligned (SA) which enables the high speed operation. The secondary bottom-gate (BG) enables to improve parameters such as on-current (ION) and the sub-threshold slope (SS-1) substantially when both gates are connected togeth...

We investigate the impact of pulse programming conditions on data-retention of 40nm × 40nm TiN\HfO2\Hf RRAM devices, focusing on the failure of tail bits. We demonstrate that retention loss tail bit is not due to out diffusion of filament constituents but by low activation-energy (Ea~0.5eV) diffusing species, which are understood as metastable Oxyg...

As CMOS scales down, hot carrier aging (HCA) scales up and can be a limiting aging process again. This has motivated re-visiting HCA, but recent works have focused on accelerated HCA by raising stress biases and there is little information on HCA under use-biases. Early works proposed that HCA mechanism under high and low biases are different, ques...

In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations br...

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with...