Giuseppe Scotti

Sapienza University of Rome | la sapienza · Department of Information Engineering, Electronics and Telecommunications

In this work, we introduce the design a 16-channel in-pixel neural analog front-end which employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventi...

In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low...

Implantable microelectrodes arrays are used to record electrical signals from surrounding neurons and have led to incredible improvements in modern neuroscience research. Digital signals resulting from conditioning and the analog-to-digital conversion of neural spikes captured by microelectrodes arrays have to be elaborated in a dedicated DSP core...

In this summary, we introduce a new design of the Latched Ring Oscillator (LRO), true-random-number-generator (TRNG) on a 7-Series FPGA, demonstrating the portability of the architecture. The novel design, combined with a novel sampling strategy, allows to enhance performance of the previous work, speeding up the throughput of about 265 times. The...

In this work we propose a 0.3V Physical Unclonable Function (PUF) exploiting body-driven feedbacks to provide digital outputs. The proposed PUF has been implemented and measured in a 130nm technology from ST-Microelectronics, showing state of the art performances.

In this paper a novel ultra-low voltage (ULV) standard-cell-based comparator which provides rail-to-rail input common-mode range (ICMR) is presented. The topology, unlike the others in the literature, uses only 2-inputs NAND gates and is able to operate with supply voltages as low as 0.15V. A detailed theoretical analysis based on transistor level...

In this paper we introduce an improved standard-cell-based voltage amplifier cell with low output resistance. The proposed amplifier cell exhibits a voltage gain whose value can be accurately set by the number of paralleled inverters, and its output static voltage is well controlled through a replica bias approach. A three-stage fully synthesizable...

This paper introduces an innovative approach to designing a mismatched current mirror with a fully unbalanced output, significantly reducing the minimum supply voltage requirements for Regulated Cascode Current Mirror (RCCM) Physical Unclonable Functions (PUFs). Leveraging body-driven feedback mechanisms, the proposed circuit reliably operates with...

In the last years several ultra-low voltage (ULV) operational transconductance amplifiers (OTAs) with supply voltages below 0.5V have been proposed in the literature. To achieve high gain, multi-stage amplifiers are frequently exploited, in spite of the complexity of design and compensation approaches, whereas cascode and regulated-cascode OTA topo...

This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologi...

Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra...

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal paramet...

In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage...

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform oc...

This paper presents a 0.3 V rail-to-rail three stage OTA. Due to the topology of the input stage, to the three gain stages and to subthreshold operation, the proposed OTA exhibits high dc gain in spite of the bulk-driven input. In addition, thanks to the adoption of two fully differential stages and the usage of an additional local common-mode feed...

In this work, a Physically Unclonable Function (PUF) based on an improved regulated cascode current mirror (IRCCM) is presented. The proposed IRCCM improves the loop-gain of the gain-boosting branch over the conventional RCCM PUF, thereby increasing the output resistance and amplifying the mismatches due to random variations. The introduction of an...

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias curr...

Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are both needed in the Privacy Preserving Mutual Autentication (PPMA) protocol, often used in IoT Applications to generate and secure cryptographic keys. Since to guarantee security of IoT nodes in an untrusted setting, the PPMA key and encrypted data must be located on...

In this brief we propose a completely novel approach to design robust analog circuits made up only of digital CMOS gates taken from conventional standard-cell libraries. The approach exploits the topology of CMOS NOT, NOR and NAND gates to derive a basic building block, namely basic amplifier ( $BA$ ) cell, which is equivalent to a CMOS inverter (...

This paper presents a True Random Number Generator (TRNG) exploiting latched-XOR (LX) gates and its implementation on a Xilinx Spartan 6 FPGA device. The proposed LX-TRNG aims at improving the Throughput (TP) of conventional ring oscillators (ROs) based TRNGs by combining the effect of latches metastability and ROs jitter. Measurements results have...

This paper presents a novel topology of ultra‐low voltage (ULV) operational transconductance amplifier (OTA), which exploits several design techniques to achieve high efficiency, symmetrical slew rate, good linearity, and robustness in spite of ultra‐low voltage operation. Simulations in a commercial 130‐nm CMOS technology with 0.3‐V supply voltage...

In this work, an ultra-low-voltage (ULV) technique to improve body-driven current mirrors is proposed. The proposed technique is employed to improve the performance of conventional differential-to-single-ended (D2S) converters which at these low voltages suffer from a low common-mode rejection ratio (CMRR). In addition, the technique aims to improv...

Volterra models allow modeling nonlinear dynamical systems, even though they require the estimation of a large number of parameters and have, consequently, potentially large computational costs. The pruning of Volterra models is thus of fundamental importance to reduce the computational costs of nonlinear calibration, and improve stability and spee...

In this brief we introduce a novel lightweight FPGA compatible Physical Unclonable Function (PUF) primitive based on XOR gates. The proposed XOR-PUF is the most compact FPGA-compatible PUF ever presented in the literature, allowing the implementation of four PUF bits in a single Configurable Logic Block (CLB) and providing very good statistical per...

In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) based on a cascade of...

A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold regime. Oscillators made up of 3, 5, and 7 stages designed in a...

This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard-cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog...

This paper presents the design of a low-noise, low-power transimpedance amplifier (TIA) for biomedical applications. The proposed TIA exploits for the first time in the literature a Switched–Resistor (SR) as the feedback element in order to achieve a digitally tunable transimpedance gain with an extremely large tuning range (higher than 80 dB) and...

In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tr...

For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based...

This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback netw...

The Switched-Resistor (S-R) technique is becoming more and more interesting to implement low-voltage low-power active- RC filters with high tuning range and front-end amplifiers for biomedical circuits and systems. This approach exploits MOS switches driven by a duty-cycle-controlled clock signal to achieve tunability of the equivalent resistance...

This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of re...

In this paper we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture and its FPGA implementation. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LRO-TRNG relies on both meta-stability and accumulated jitter as...

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amp...

Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control...

In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most im...

The Switched-Resistor (S-R) approach is gaining popularity among integrated circuits designers because it allows to implement very high equivalent resistances, and thus very large time constants, in CMOS circuits. In this paper, we present an in-depth analysis of the S-R technique and propose a novel detailed model which allows to accurately predic...

A novel architecture and design approach which make it possible to boost the bandwidth and slewrate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, ba...

High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less fi...

The switched-resistor (S-R) approach is becoming more and more popular among integrated circuits designers because it allows the implementation of very high equivalent resistances in CMOS circuits. When using this technique, the value of a reference poly resistor is multiplied by a factor dependent on the duty cycle of the clock signal. To achieve...

With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced mo...

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascad...

In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and...

In this paper we present a novel Operational Transconductance Amplifier (OTA) topology based on a dual path body-driven input stage, exploiting body-driven current mirror active load and targeting ultra-low-power (ULP), ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node a...

Computation intensive kernels, such as convolutions, matrix multiplication and Fourier transform, are fundamental to edge-computing AI, signal processing and cryptographic applications. Interleaved-Multi-Threading (IMT) processor cores are interesting to pursue energy efficiency and low hardware cost for edge-computing, yet they need hardware accel...

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralo...

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeli...

A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a...

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 ( DIV2 ) cell is introduced. We demonstrate...

In this work, we present a low-power 2nd order band-pass filter for neural recording applications. The central frequency of the passband is set to 375Hz and the quality factor to 5 to properly process the neural signals related to the onset of epileptic seizure, and to strongly attenuate all the out of band biological signals and electrical disturb...

In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) which can be applied to a generic MCML gate (i.e., with a fan-in higher than two). The idea is implemented by alternating NMOS and PMOS differential pairs and properly introducing current mirrors between the adjacent levels of logic. The proposed appr...

Convolutional computation kernels are fundamental to today's edge computing applications. Interleaved-Multi-Threading (IMT) processor cores are an interesting approach to pursue the highest energy efficiency and lowest hardware cost in edge computing systems, yet they need hardware acceleration schemes to deal with heavy computational workloads lik...

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation, and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole...

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all...

In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or...

In this paper we present propagation delay models for MCML gates with resistor- or triode-PMOS-based output I-V conversion. The dependence of the parasitic capacitance of triode PMOS devices is accurately evaluated for the first time in the literature. The proposed models are able to accurately predict the propagation delay as a function of the bia...

An innovative low‐voltage low‐power complementary metal‐oxide‐semiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate‐driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch....

This paper presents ultra low-voltage CML D-latch and D-Flip-Flop topologies in deeply scaled CMOS technologies, able to operate at a supply voltage as low as 0.5V (no other CML D-Flip-Flops are able to operate at such a low supply voltage). The topology is based on a modified version of the Folded D-Latch, recently proposed by the authors. In the...

This paper presents experimental results on a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions. The proposed logic family is based on the time enclosed logic (TEL) encoding and can be viewed as an improvement of the delay based dual rail pre-charge logic (DDPL) logic style. The DDPL logic gates...

A new very low-voltage topology to implement MOS current mode logic (MCML) XOR gates is proposed in this paper. Instead of stacking several level oftransistors to implement a two inputs XOR gate, a p-type differential pair is used to steer the current in n-type differential pairs through current mirrors. The proposed topology allows to reduce the m...

The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose diff...

Power analysis attacks (PAAs), a class of side-channel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a register-transfer level (RTL) countermeasure to increase the security of cryptographic...

This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and th...

Latest nanometer CMOS technology nodes have highlighted new issues in security of cryptographic hardware implementations. The constant growth of the static power consumption has led to a new class of side-channel attacks. Common attacks exploiting static power use an univariate approach to recover information from cryptographic engines. In our work...

In this paper, a novel framework is introduced to estimate the max-delay variability in logic paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of the additional cycle time margin imposed by random (local) variations. The framework provides the designer with a deep insight into the main variability contributi...

This paper presents a CMOS operational transconductance amplifier (OTA), suitable for sub-1-V supply applications, whose (input) common-mode voltage can be set to (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> + V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www....

The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition...

A new class of template attacks aiming at recovering the secret key of a cryptographic core from measurements of its static power consumption is presented in this paper. These attacks exploit the dependence of the static current of Complementary metal–oxide–semiconductor Integrated Circuits on the input vector and the maximum likelihood decision ru...

La coppia differenziale è uno dei blocchi elementari più importanti nella realizzazione di circuiti integrati; su essa sono basati sottosistemi fondamentali quali amplificatori, moltiplicatori, mixer, transconduttori, filtri, ecc. In questo lavoro si è studiata una soluzione operante a bassissima tensione di alimentazione (<1V) per applicazioni low...

We investigate AM/PM distortion models and compare them with baseband (BB) Volterra models. We show that the AM/PM model can be considered a special case of memoryless baseband Volterra models, and that adding memory can improve modeling accuracy by allowing the simulation of more complex nonlinearities. We report models of an LNA, a downconversion...

The possibility of recovering sensible information through the observation of dynamic power consumption of a cryptographic device is a critical issue in security applications. As it has been widely demonstrated in the literature, it is possible to reveal the secret keys of a cryptographic device exploiting the information leaked by the implementati...

In this work, the implementation of the PRESENT-80 block cipher in a 40nm CMOS technology, and its vulnerability to Side Channel Attacks Exploiting Static Power is investigated. In the last two decades, several countermeasures to thwart DPA/CPA attacks based on the exploitation of dynamic power consumption have been proposed. In particular, WDDL lo...

In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice simulations of static power have been carried out to show that the coefficient of variation of nanometer logic gates is increasing with the scaling of CMOS technology...

A continuous-time complementary metal-oxide-semiconductor differential pair that does not require the traditional tail current source as a way to control the direct current and common-mode current is presented. Compared with a p-channel long-tailed pair, the proposed non-tailed solution operates under a higher maximum input common-mode voltage that...

Electrical and capacitive mismatches are outstanding issues in modern submicron technologies, and must be considered already during the design steps. In this work, we propose a novel hardware countermeasure based on the combination of a circuit- and a system-level methodology, which helps to reduce the data dependence of the instantaneous power con...

SUMMARYA design procedure for high-order continuous-time intermediate-frequency band-pass filters based on the cascade of low-Q biquadratic cells is presented. The approach is well suited for integrated-circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivit...

The paper deals with the opportunity to introduce “Not strictly TEM waves” Synthetic detection Method (NTSM), consisting in a Three Axis Digital Beam Processing (3ADBP), to enhance the performances of radio telescope and sensor systems. Current Radio Telescopes generally use the classic 3D “TEM waves” approximation Detection Method, which consists...

The paper deals with a possible use of the feed array present in a large antenna system, as a layer for measuring the antenna performance with a self-test procedure and a possible way to correct residual errors of the Antenna geometry and of the antenna distortions. Focus has been concentrated on a few key critical elements of a possible feed array...

In this paper we present a methodology to calibrate and correct frequency-dependent errors in phased-array antennas with large signal bandwidth and large size. If the receivers are not narrow-band, the hypotheses of constant gain and group delay are not valid. If the frequency responses of the receivers are affected by mismatches, this will also im...

The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current,...

A novel topology of lossy equalizer with impedance transformation and stabilization capability is presented, which allows the design of broadband very high-linearity and high-power amplifiers. Design equations are presented and used to design a 1-2.4 GHz 60W composite amplifier exploiting push-pull configuration.

In this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-channel attacks against cryptographic circuits, has been demonstrated on a case study. LPA attacks have been mounted against a bit slice implementation of the Serpent block cipher. After having measured the leakage contribution of a bit slice unit inside the process...

Two novel process variations aware, necessary and sufficient conditions suitable for implementation in CAD optimizers are proposed to check amplifiers stability. Case studies are presented, showing that the new criteria allow robust amplifier design, under variation of active device immittance parameters in pre‐specified rectangular regions, due to...

We analyze the effects of relative mismatches in transconductances and in capacitances onto the magnitude of the Gm-C biquad filter section. It is confirmed that deviation from the ideal magnitude increases with Q and with mismatches, being those associated with transcondunctances the relevant ones. The obtained data can be used at an early design...

Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits in order to prevent Power Analysis (PA) attacks. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions, which all...

We present an adaptive frequency compensation technique providing maximum bandwidth closed-loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed-loop bandwidth is kept ideally constant irrespective of the...