Neural network controller based sequential switch cascaded H-bridge multilevel inverter

Abstract

This paper presents a novel cascaded multilevel inverter structure with reduced devices. This structure is termed as sequential switch cascaded multilevel inverter. The basic asymmetrical hybrid circuit is described and is capable of generating 17 voltage levels. The various modes of deriving 17 levels are explained and the proposed topology is compared with existing topologies in various aspects. Neural network controller can be used to generate the gating pulses. The algorithm can be trained online by using back propagation algorithm and also an algorithm to determine the number of levels, maximum voltage ratings and power loss is explained. The simulation can be done by MATLAB Simulink.

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International Journal of Engineering & Technology, 7 (2.8) (2018) 592-598
International Journal of Engineering & Technology
Website: www.sciencepubco.com/index.php/IJET
Research Paper
Neural network controller based sequential switch
cascaded H-bridge multilevel inverter
M Ramya1*, P Usha Rani2 , G.Ganesan @ Subramanian3, K.Ramash Kumar4
1Assistant Professor, E.G.S. Pillay Engineering College, Nagapattinam, Tamilnadu, India
2Professor, R..M.D. Engineering College, Thiruvallur, Tamilnadu, India
3Assistant Professor, E.G.S. Pillay Engineering College, Nagapattinam, Tamilnadu, India
4Professor, Karpagam College of Engineering, Coimbatore, Tamilnadu, India
*Corresponding Author Email: ramyaegsp.eee@gmail.com
Abstract
This paper presents a novel cascaded multilevel inverter structure with reduced devices. This structure is termed as sequential switch
cascaded multilevel inverter. The basic asymmetrical hybrid circuit is described and is capable of generating 17 voltage levels. The various
modes of deriving 17 levels are explained and the proposed topology is compared with existing topologies in various aspects. Neural network
controller can be used to generate the gating pulses. The algorithm can be trained online by using back propagation algorithm and also an
algorithm to determine the number of levels, maximum voltage ratings and power loss is explained. The simulation can be done by
MATLAB Simulink.
1. Introduction
The scope of multilevel inverters has received more attention
because of their high power handling capacity and they can be
successfully implemented in medium and high power applications.
Recently multilevel inverters are popular in most of power
electronic applications due to its high power handling ability,
modularity, and superior harmonic characteristics. An array of
power semiconductor devices and dc voltage sources are used to
generate stepped voltages. Also they are capable of producing
output with high quality, reduced harmonics and switching losses.
Among three basic types of multilevel inverter namely diode
clamped, flying capacitor (FC), cascaded H-Bridge (CHB), the CHB
topology uses reduced number of power switches. And to produce
high voltage levels two switching configuration are used. They are
termed as symmetrical and asymmetrical configuration. In
asymmetrical switching by properly introducing the dc voltage
proportions successfully the number of components can be
reduced with increase in output voltage level.Asymmetrical
cascaded MLI with trinary dc sources produce high number of
levels than binary switching. Currently researchers concentrating on
developing new structures of cascaded multilevel inverter to reduce
number of power components [1]-[3]. The basic symmetrical
topology presented in [4] requires (2X+1) output levels for X
number of H-Bridges.
The major drawback of this symmetrical structure is its increased
number of components for higher levels as it uses same dc voltages
for all H-Bridges. A new symmetrical multilevel inverter has been
presented in [5] that use single and double source sub multilevel
units. The series and parallel combinations of switches reduce the
total conducting switches in each level.
An asymmetrical configuration with series/parallel conversion of
sources presented in [6].This topology is implemented with multi
output boost converter. The drawback is when number of level
increases the variety of dc sources increases. In article [7]
asymmetrical cascaded H-Bridge with different switching frequency
for different H-Bridges has been presented. The capacitor voltage
balancing technique is also discussed but increases the voltage stress
on each conducting switch. Modular Multilevel Converter (MMC)
configuration presented in [8],[9] can be easily extended to higher
levels but it requires large number of switches. And also neutral
point clamped (NPC) technique introduced in1981 uses series
connected capacitors at the input side. The main problem is
capacitor voltage balancing [10],[11].
Various algorithms in determining values of sources have been
presented in [12]. A trinary based algorithm is presented in [13] that
needs minimum components and also many structures were
developed to reduce number of switches , driver units, dc sources ,
maximum voltage rating. In [14]-[16] fundamental structure have
been developed but number of switches and voltage rating of
switches are high. A new topology is presented in [17] and three
algorithms have been explained that reduces the number of
components used. But here the variety of dc sources increases. A
fundamental topology based on developed H- Bridges presented in
literature [18] use unidirectional switches and also an algorithm to
determine voltage rating, number of sources to analyze cost of the
inverter is presented. An asymmetric topology with less number of
main switches has been presented with concentration on THD
reduction [19],[20]. In asymmetric switching with binary hybrid
multilevel inverter produces higher number of levels than
symmetric type [21].
In this paper a fundamental topology of multilevel inverter
structure which uses reduced number of switches, dc sources. The
basic unit is capable of generating seventeen voltage levels and
this structure can be extended to higher number of levels.
The Insulated Gate Bipolar junction Transistor (IGBT) with
antiparallel diode combination is used as switch. This sequential
switch cascaded multilevel topology is compared with existing
topologies presented in literature [10]-[18] in various aspects such
as maximum blocking voltage, number of dc sources and number
of IGBTs. The performance of the inverter is checked with

International Journal of Engineering & Technology
593
MATLAB Simulation. Asymmetrical MLI, Interline Dynamic
voltage restorer are discussed in [33-37]. Dc-dc converters using
controllers [22-32].
2. Proposed Sequential Switch Cascaded
Multilevel Inverter
Fig. 1 shows the basic sequential switch cascaded multilevel inverter
(SSCMLI). It consists of six unidirectional switches (Su1 , Su2 , Su3 ,
Su4 , Sun , Sum ) and two bidirectional switches (Sb1 , Sb1 ) , four dc
sources (Vd1 , Vd2 ) connected with load. Two dc sources in same leg
has same value. The insulated Gate Bipolar Junction Transistor
(IGBT) with antiparallel diode is used as switch. The fundamental
unit can be extended to higher number of levels by increasing the
number of bidirectional switches in each leg
.
Fig. 1: Proposed basic sequential switch cascaded MLI
The basic unit is capable of generating 17 levels. The various
modes of operation for generating all voltage levels is given in fig
2(a)- fig 2(q). During mode-I the conducting switches are Sun, Su1
and Sb1.Here the subscript ‘u’ represents the corresponding switch
isunidirectional and ‘b’ represents bidirectional switch. The output
voltage at the end of mode-I is V0= Vd1. The switches Sun, Su3 and
Sb2 conducts,V0= Vd2 during mode-II. In mode-III, the switches Sun,
Sun1 and Su2 are conducting and output voltage is V0=2Vd1 .when
the switches Sun, Su3 and Su4 are conducting the output voltage is
V0=2 Vd2.During mode-V, the switches Sun, Sb1 and Sb2 are
conducting, V0=(Vd1+Vd2). In mode –VI, the switches Su1, Sun and
Sb2 are turned on to give output voltage V0= (2Vd1+Vd2).
During mode VII the switches Sb1, Su4 and Sun are conducting and
voltage across load is V0=(Vd1+2 Vd2). During mode VIII the
conducting IGBTs are Su1, Su4 and V0= (2Vd1+2 Vd2). From mode-I
to mode-VIII, the output levels are positive and from mode-IX to
mode-XVII the output levels are negative. In order to avoid short
circuit the switches in the same leg cannot be turned on at the same
time. Thus the switches Su1 and Su3 should not be turned on at the
same time. Similarlythe closing of switchesSu4 and Su2 at the same
time should be avoided and also the simultaneous turn on Sun and
Sum must be avoided. In order to get maximum levels in the output
unequal dc voltages are chosen such that the dc sources in the same
leg are same but different legs are different. The basic proposed unit
can be connected in m number of series connected units to generate
more number of levels. For example the value of series connected
basic unit is taken as two it is possible to extract 81 levels in the
output.
Fig. 2(a): Mode-I (V0= Vd1)
Fig. 2(b): Mode-II (V0= Vd2)
Fig. 2(c): Mode-III (V0=2 Vd1)
Fig. 2(d): Mode-IV (V0=2 Vd2)
Fig. 2(e): Mode-V (V0=(Vd1+Vd2)

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International Journal of Engineering & Technology
Fig. 2(f): Mode-VI (V0= (2Vd1+Vd2)
Fig. 2(g): Mode-VII (V0=(Vd1+2 Vd2)
Fig. 2(h): Mode-VIII (V0=(2Vd1+2 Vd2)
Fig. 2(i): Mode- IX (V0=0)
Fig. 2(j): Mode-X (V0= - Vd1)
Fig. 2(k): Mode-XI (V0= - Vd2)
Fig. 2(l): Mode-XII (V0= -2 Vd1)
Fig. 2(m): Mode-XIII (V0= -2 Vd2 )
Fig. 2(n): Mode-XIV (V0= -(Vd1+Vd2))
Fig. 2(o): Mode-XV (V0= -(2Vd1+Vd2)

International Journal of Engineering & Technology
595
Fig. 2(p): Mode-XVI (V0= -(Vd1+2 Vd2))
Fig. 2(q): Mode-XVII (V0= -(2Vd1+2 Vd2)
Table-I summerizes the switching states of sequential switch
cascaded multilevel inverter.Here 0 represents switch is in open
condition and 1 represents switch is in closed position. In order to
get zero output voltage either the switching combination Su1, Su4 and
Sun or Su2, Su3 and Sum are used. For obtaining positive voltages the
switching combination must contain Sun as one of the switch and to
obtain negative voltage levels the switching combination should
contain Sum as one of the switch. When the switch is open the
current through the switch is zero and when switch is closed, the
maximum current is equal to the load current.
Table 1: Output Voltage And Switching States of the Inverter
Switching states
Vo
Su1
Su2
Su3
Su4
Sb1
Sb2
Sun
Sum
0
1
0
0
1
0
0
1
Vd1
0
0
1
0
0
1
0
1
Vd2
1
1
0
0
0
0
0
1
2 Vd1
0
0
1
1
0
0
0
1
2 Vd2
0
0
0
0
1
1
0
1
(Vd1+Vd2)
1
0
0
0
0
1
0
1
(2Vd1+Vd2)
0
0
0
1
1
0
0
1
(Vd1+2 Vd2)
1
0
0
1
0
0
0
1
(2Vd1+2 Vd2)
1
0
0
1
0
0
1
0
0
0
0
0
1
1
0
1
0
- Vd1
1
0
0
0
0
1
1
0
- Vd2
0
0
1
1
0
0
1
0
-2 Vd1
1
1
0
0
0
0
1
0
-2 Vd2
0
0
0
0
1
1
1
0
-(Vd1+Vd2)
0
0
1
0
0
1
1
0
-(2Vd1+Vd2)
0
1
0
0
1
0
1
0
-(Vd1+2 Vd2)
0
0
1
1
0
0
1
0
-(2Vd1+2 Vd2)
3. Algorithm to Find Magnitudes of Dc
Voltages & Maximum Voltage Rating
In this topology the dc voltage on each leg is same. The dc voltages
on leg 1 is Vd1 and leg 2 is Vd2 which ia obtained from following
equations
(1)
(2)
Where nb represents number of bidirectional switch on each leg. The
maximum output voltage Vom is given by,
(3)
In general,
(4)
(5)
The total number of level (Nl) can be found as
(6)
The number of IGBTs are
(7)
The number of driver units are
(8)
The number of sources are calculated as follows,
(9)
In order to analyze cost of the inverter an important parameter is
considered which maximum voltage rating on switches.
(10)
Where MVRus and MVRbsrepresents maximum voltage rating of
unidirectional switches and bidirectional switches respectively.
MVRs total maximum rating of switches. MVRus is calculated as
follows,
(11)
Where Vsum,Vsun,Vsu1, Vsu2,Vsu3 ,Vsu4 are values of corresponding
voltages on switches Sun,Sum, Su1,Su2,Su3,Su4 respectively.
(12)
(13)
(14)
Using the above three equations
(15)
The maximum voltage rating of bidirectional switches can be found
as,
(16)
The switch is comprised of an IGBT with diodes.. Hence while
calculating losses (conduction and switching) parameters related to
IGBT and diode are considered. The conduction losses for IGBT
and Diode are calculated as follows,
(17)
(18)
The average conduction loss of inverter is
(20)
dcbd VnV )2(
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dc
1m
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2
b1dm V)7n8n2(V 

12 )2( dmbdm VnV 
m
bl nnN )782( 2
dcdVV 
1
)64(  bIG nmN
)62(  bD nmN
)22(  bs nmN
bsussMVRMVRMVR 
4321 sususususumsunus VVVVVVMVR 
))(1( 21 ddbsunsum VVnVV 
131 )1( dbsusu VnVV 
242 )1( dbsusu VnVV 
))(1(4 21 ddbus VVnMVR 
)( 21 ddbs VVMVR 
   
 
 
titiRVtIGBTP IIcon
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
   
 
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titiRVtDP didicon 
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0dttDPtNtIGBTPtNP conDconIcon 



596
International Journal of Engineering & Technology
Where NI(t) and ND(t) represents number of conducting IGBTs
and diodes at instant t
The switching loss is given by
(21)
Where
(22)
(23)
Et,off,s, Et,on,s are energy loss during turn off and turn on. Non,S and
Noff,S represents number of turn on and turn off of switch S in one
fundamental cycle. The total loss is given by
(24)
4. Neural Network Controller
The appropriate switching angles of PWM inverter for a given
modulation index can be generated by using NN. While using
ANN controller it is necessary to train the NN either online or
offline. During online training the weights and biases can be
changed which is more suitable for nonlinear conditions [19]. But
in offline training the weights and biases are fixed. There are two
types ofcontrol algorithms can be used. They are forward
propagation algorithm and backward propagation algorithm [18].
A typical multilayer NN consists of an input layer, a middle layer,
and an output layer. Here NN has single input layer, one hidden
layer and n output layer. The output of the neuron is represented
by,
(25)
Each of the input signal flows through gain or weight. All these
input weighted signals are accumulated by the summing node and
then passes to the output through transfer function. The transfer
function normally used will be sigmoid, inverse-tan, hyperbolic, or
Gaussian type.
The expression for transfer function (sigmoid) used here is given
by
(26)
The Gaussian transfer function is expressed as
(27)
Back propagation algorithm is most commonly used in many
applications. The figure 2 shows training of ANN for selective
harmonic elimination. Modulation index is given as input and
switching angle is taken as output. The output is represented by
(28)
The steps in training algorithm can be summarized as follows,
 Assign arbitrary weights to the hidden layer and output layer.
Input layer is assigned with unity weight.
 Modulation index is given as input and back propagation error
has been determined by
E=Vt -Vo
 The weights can be changed based on the propagation error. the
change in weight is given by
Δw = δ VoE (29)
andδ , E represents learning rate and error.
 The new weights are determined as w= w + Δw
 The training process has been repeated until the error has
reduced to least value.
Fig. 3: Block diagram of neural network controller
5. Simulation Results
The simulation can be done by using MATLAB Simulink
software. The performance of the proposed SSCMLI can be tested
by simulation. Fundamental switching technique is used to
generate the gating pulses of the inverter. The values of dc sources
are Vd1=25V and Vd2=75V and outputfrequency is 50 Hz.The load
is R-L with values of R=110Ὠ and L=45 mH. The output voltage
is indicated in fig (5)
Fig. 4: Simulation diagram of proposed SSCMLI
Fig. 5: SSCMLI Output voltage
  
  









 SSon Soff
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j
N
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   
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,
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
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

International Journal of Engineering & Technology
597
Fig. 6: FFT Analysis of proposed SSCMLI
Fig. 7: Switching pulses of switches (a) switch Su1 (b) switch Su2(c) switch
Su3 (d) switch Su4 (e) switch Sun (f) switch Sum (g) switch Sb1
(h) switch Sb2(i) switch Su1
6. Conclusion
A novel structure of cascaded multilevel inverter is proposed. In
this paper it is termed as sequential switch cascaded multilevel
inverter (SSCMLI).The fundamental unit is a 17 level inverter.
The structure can be extended to high number of levels. The gating
signals are generated by neural network controller and back
propagation algorithm is used to train the controller online.An
algorithm to find the number of levels number of main switches,
blocking voltages across the switches, power loss, number of DC
sources and number of driver circuit has been proposed. The
proposed SSCMLI requires 6 unidirectional switches, two
bidirectional switches and four DC sources. The simulation result
shows the performance of the SSCMLI for various load changes
and change in modulation indices. The inverter has less voltage
harmonic distortion which is 5.51%.
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