Fabio Sebastiano

Delft University of Technology | TU · Department of Quantum and Computer Engineering; Department of Microelectronics; QuTech

This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with...

This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, th...

In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This paper introduces a theoretical framework to evaluate the effect of vari...

The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS proc...

Quantum processors based on color centers in diamond are promising candidates for future large-scale quantum computers thanks to their flexible optical interface, (relatively) high operating temperature, and high-fidelity operation. Similar to other quantum-computing platforms, the electrical interface required to control and read out such qubits m...

Despite NISQ devices being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed to enable successful algorithm executions. Not so much attention has been paid to mapping and compilation implementations for spin-qubit quantum processors due to the scarce availability of experimental devices and t...

Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum computers are limited by errors that may only partially be mitigated by developing higher-quality qubits. Quantum error correction~(QEC) will thus be necessary to ensure faul...

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6–8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circui...

This letter presents the first clock and data recovery (CDR) system operating at 4.2 K designed for quantum computing (QC) applications. By considering the benefits and challenges of cryogenic operation, a dedicated analog CDR structure is employed so as to maintain high performance at 300 and 4.2 K. The CDR incorporates a new complementary charge-...

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an int...

Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum computers are limited by errors that may only partially be mitigated by developing higher-quality qubits. Quantum error correction (QEC) will thus be necessary to ensure faul...

As big strides were being made in many science fields in the 1970s and 80s, faster computation for solving problems in molecular biology, semiconductor technology, aeronautics, particle physics, etc., was at the forefront of research. Parallel and super-computers were introduced, which enabled problems of a higher level of complexity to be solved....

In most qubit realizations, prototype devices are available and are already utilized in both industry and academic research. Despite being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed for enabling successful algorithm executions during the NISQ era, targeting mostly technologies with hig...

Over the past decade, significant progress in quantum technologies has been made and, hence, engineering of these systems has become an important research area. Many researchers have become interested in studying ways in which classical integrated circuits can be used to complement quantum mechanical systems, enabling more compact, performant, and/...

Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without problematic leakage currents, thanks to the larger diode turn-on voltage at cryogenic temperatures. As a...

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2 $\times$ time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuous-time input signal by windowed integration, thus avoiding the traditional sample-...

This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a new P...

One of the main bottlenecks in the pursuit of a large-scale–chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture tha...

Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardwa...

We demonstrate a 36$\times$36 gate electrode crossbar that supports 648 narrow-channel field effect transistors (FET) for gate-defined quantum dots, with a quadratic increase in quantum dot count upon a linear increase in control lines. The crossbar is fabricated on an industrial $^{28}$Si-MOS stack and shows 100% FET yield at cryogenic temperature...

Quantum error correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardwa...

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog P...

This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 down to 4.2. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. S...

One of the main bottlenecks in the pursuit of a large-scale--chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture th...

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the refe...

This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectivel...

The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications¹. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a d...

Quantum computing could potentially offer faster solutions for some of today's classically intractable problems using quantum processors as computational support for quantum algorithms [1]. Quantum processors, in the most frequent embodiment, comprise an array of quantum bits (qubits), the fundamental computational unit of a quantum computer. Unlik...

Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/outpu...

Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scala...

The most promising quantum algorithms require quantum processors hosting millions of quantum bits when targeting practical applications. A major challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, a major bottleneck appears between the quantum chip in a dilution refrigerato...

The design of a large-scale quantum computer requires co-optimization of both the quantum bits (qubits) and their control electronics. This work presents the first systematic design of such a controller to simultaneously and accurately manipulate the states of multiple spin qubits or transmons. By employing both analytical and simulation techniques...

We present a digital cell library optimized for 4.2 K to create controllers that keep quantum processors coherent and entangled. The library, implemented on a standard 40nm-CMOS technology, was employed in the creation of the first 4.2 K RISC-V processor. It has achieved a minimum supply voltage of 590mV, energy-delay product of 37fJ/MHz, and maxim...

In the 2010s quantum technologies have emerged as a compelling complement to classical technologies for a number of applications, including quantum sensing, metrology, imaging, communications, security, and computing.

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2 to 300. Ano...

This paper presents the characterization and modeling of microwave passive components in TSMC 40-nm bulk CMOS, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperatures (4.2 K). To extract the parameters of the passive components, the pad parasitics were de-embedded from the test structures using an...

Quantum computers require classical electronics to ensure fault-tolerant operation. To address compactness and scalability, it was proposed to implement such electronics as integrated circuits operating at cryogenic temperatures close to those at which quantum bits (qubits) operate. Circulators are among the most common blocks used in the qubit rea...

This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased ΣΔ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maxi...

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 down to 4.2. The device parameters relevant for mismatch, i.e. the threshold voltage and the current fact...

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility g...

This paper presents the characterization of microwave passive components, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperature (4.2 K). The variations in capacitance, inductance and quality factor are explained in relation to the temperature dependence of the physical parameters and the resulting...

We propose a phase-insensitive parametric amplifier featuring image cancellation and a doubly-tuned transformer to enhance its bandwidth. Exploiting the reduced loss of passive components at cryogenic temperatures, the experimental characterization of a prototype shows a power gain of 9 dB with a bandwidth of 1.85 GHz for a pump frequency of 15.6 G...

Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/outpu...

A read-out scheme inspired by dynamic random access memory could help deliver scalable quantum computers.

Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronic...

Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronics required to interfac...

The increasing interest in electronics specifically designed to control quantum processors is currently driven by the quest for large-scale quantum computing. A promising approach is emerging based on the use of CMOS devices operating at deep-cryogenic temperatures, and several essential components have been demonstrated to operate at such temperat...

This paper presents a 7-MHz CMOS RC frequency reference. It consists of a frequency-locked loop in which the output frequency of a digitally controlled oscillator (DCO) is locked to the combined phase shifts of two independent RC (Wien bridge) filters, each employing resistors with complementary temperature coefficients. The filters are driven by t...

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ΔΣ ADC. Compared to previous zoom ADCs, faster reference updates relax the lo...

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS1...

Quantum processors rely on classical electronic controllers to manipulate and read out the quantum state. As the performance of the quantum processor improves, non-idealities in the classical controller can become the performance bottleneck for the whole quantum computer. To prevent such limitation, this paper presents a systematic study of the imp...

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread. However, at deep-cryogenic temperatures, the performance of BJTs deteriorates due to a signi...

This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm² in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be present...

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum compu...

Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum...

Even the quantum simulation of simple molecules such as Fe$_2$S$_2$ requires more than 10$^6$ qubits. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it provides the capability of nanometric, serial and industrial quality fabrication. The maximu...

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The p...

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art are...

An array of temperature sensors based on the thermal diffusivity (TD) of bulk silicon has been realized in a standard 40-nm CMOS process. In each TD sensor, a highly digital voltage-controlled oscillator-based ΣΔ ADC digitizes the temperature-dependent phase shift of an electrothermal filter (ETF). A phase calibration scheme is used to cancel the A...

VCO-based phase-domain ΣΔ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional ΣΔ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the a...