Eric Beyne

imec · STS

In this article, the reliability assessment of a 2.5-D metal–insulator–metal (MIM) capacitor, built in a thicker back-end of line layer using a 23-nm-thick ALD-deposited Al-doped HfO $_\text{2}$ high- $\kappa$ dielectric, is performed using time-dependent dielectric breakdown (TDDB) measurements. This capacitor, compatible with back-side power de...

With ever increasing integration density of electronic components, the demand for cooling solutions capable of removing the heat generated by such systems grows along with it. It has been shown that a viable answer to this demand is the use of direct liquid jet impingement. While this method can generally be scaled to the cooling of large areas, th...

Hybrid Cu/dielectric bonding is a well-established technology for Wafer-To-Wafer (W2W) bonding, but it is challenging to apply this technology to Die-To-Wafer (D2W) bonding. Very small particles on the die or wafer can lead to voids/non-bonded regions. Processes to clean and activate wafers for hybrid W2W are quite mature, but it is very challengin...

Customer need for faster electronic products, with enhanced functionalities and smaller form factor is driving the growth of the microelectronic industry. As the traditional more Moore approach is slowing down due to the exponential cost of silicon scaling and the lowers yields [1], a chiplet-based future is being adopted [2, 3]. Chiplets enable mo...

As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconne...

A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need f...

A novel technique to accurately characterize interconnects with general, piecewise homogeneous material parameters and arbitrary polygonal cross-sections is presented. To compute the per-unit-of-length complex inductance and capacitance matrices of the considered structures, we apply a boundary integral equation framework, invoking a Dirichlet-to-N...

Atomic layer-deposited (ALD) inorganic films were processed on top of copper metal lines in a polymer-based redistribution layer (RDL). The primary objective was to develop capping layers thinner than 15 nm to prevent copper oxidation. Due to their uniformity and high density, ALD layers are established permeation barriers. Nonetheless, owing to th...

In state-of-the-art interconnect design, topologies including magnetic materials, such as the so-called superlattice conductors, are rapidly emerging as a novel strategy to handle the challenges associated with the evolution toward higher operating frequencies and integration densities. Consequently, it is imperative that the newly developed full-w...

When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. Gate clustering is even more important for netlist partitioning targeting 3D system integration. In this paper, we make the argument that the ch...

Multi-dies stack 3D-ICs are an extension of traditional 2-dies 3D-ICs to address the memory wall and footprint problems. This paper presents a complete Place-and-Route (PnR) flow to enable 3-dies stacked 3D-ICs from netlist partitioning to timing analysis, including original cross-dies co-optimization steps. The proposed flow is based on Integrity...

To obtain reliable 3D stacking, a void-free bonding interface should be obtained during wafer-to-wafer direct bonding. Historically, SiO2 is the most studied dielectric layer for direct bonding applications, and it is reported to form voids at the interface. Recently, SiCN has raised as a new candidate for bonding layer. Further understanding of th...

We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also cont...

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1- $\mathrm {W}/{\mathrm {mm}}^{2}$ power-density target for high-performance computing (HPC) systems, a 25-high- $Q$ -factor (300 MHz), 150- $\mu \text{m}$ -t...

Wafer-to-wafer Cu hybrid bonding relies on non-elastic Cu-pad expansion to achieve permanent CuCu pad bonding between the bonded wafers. Understanding the mechanism and being able to predict the amount of Cu expansion and the mechanism of this Cu expansion is the key for defining the chemical-mechanical polishing specifications and process window,...

Hybrid organic–inorganic and inorganic multilayer films were deposited using a combination of CVD and ALD processes to develop an ultra-thin barrier to prevent copper oxidation in a polymer-based RDL technology. ALD layers are known to be effective permeation barriers due to their uniformity and pinhole-free morphology. However, the low deposition...

The use of eutectic Sn-Cu alloys in packaging applications in microelectronics industry is not something entirely new. However, this alloy was mostly used in large features and fabricated using metal powders and metallurgical deposition techniques. The diameter of an individual grain of the eutectic Sn-Cu powder is typically similar in size to the...

Achieving a void-free bonding interface is an important requirement for the wafer-to-wafer direct bonding process. The two main potential mechanisms for void formation at the interface are (i) void formation induced by gas, such as condensation by-products caused by the bonding process or outgassing of trapped precursors, and (ii) void formation in...

We present a $\mu \text{m}$ -thin-profile power delivery solution including a charge pump with integrated passives. Targeting 1 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> or higher power density, a 2.5-D high-density metal-insulator-metal (MIM) capacitor deposited on high aspect rat...

We used the surface planer process to minimize the within-die and within-wafer nonuniformity caused by the nonoptimized Cu pillar and Si thinning processes. The height variation of the planarized Cu pillars was 3.5% of the within-wafer uniformity in a 300-mm wafer, which represents a substantial reduction of the post-electrodeposition height variat...

Jet impingement cooling with distributed outlet configuration is regarded as an efficient cooling solution for high-performance systems. This work develops the Nusselt number Nu f - R e d and pressure drop k -factor correlations for microscale multi-jet impingement cooling with alternating feeding and draining jets. An extensive design of experimen...

Abstract—This letter describes the use of area-selective electrolessCu deposition for topographycontrol of Cu-SiCN hybrid bonding pads. The electroless deposition of Cu allows one to obtain protrusions on hybrid bonding Cu pads without further polishing optimization. A recessed Cu pad after chemical mechanical polishing becomes a protrusion after e...

We report optical and electron beam-based fault isolation approaches for short and open defects in nanometer scale through silicon via (TSV) interconnects (180×250 nm, 500 nm height). Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage co...

Process flows for memory stacking or other heterogeneous integration schemes benefit from die bonding on a thinned silicon wafer 100 μm or less. In scenarios where a thinned device wafer contains features such as microbumps or Cu pillars, a carrier and temporary bonding material (TBM) facilitate the support of the fragile landing wafer during therm...

For a time, each new processor churned out more waste heat than the last. Had these chips kept on the trajectory they were following in the early 2000s, they would soon have packed about 6,400 watts onto each square centimeter-the power flux on the surface of the sun.

We report a scanning photocapacitance microscopy technique for the localization of open electrical defects in hybrid bonding wafer-to-wafer (W2W) interconnect structures for 3-D system integration. Whereas the well-known optical beam induced resistance change (OBIRCH) method is effective for the localization of resistive opens and shorts, it cannot...

In this work, we present the analytical model of buck converter with 3-D in-package air-core inductor ( $150~\mu \text{m}$ thick). To optimize the power efficiency at a targeted power density, models including 3-D inductor and power switches are developed. Compared to 3-D electromagnetic (EM) simulation, the proposed inductor model has a modeling...

We present an IR-drop analysis of hybrid bonded 3D-ICs Power Delivery Network with backside metals and buried power rail. Two different options for the backside to frontside connectivity are included: µTSVs and nTSVs (respec-tively 0.5µm, 0.09µm diameter and 1Ω, 10Ω nominal resistance). Further, Hybrid Bonding CuPads are used to deliver power to th...

(1) 2.5D MIM: capacitance density (86 fF/μm^2, 1.36-V bias/10 year/100℃), 0.1% parasitic impact, and small form factor (~μm thick) (2) 3D (or 2.5D) power IC, 1/2 ratio, 91.5% power-delivery-efficiency at 1 W/mm^2

(1) backside LDMOS: 1.5x lower QON∙RON, 4.9x lower output COSS, low-loss interconnect to BS-delivery system, (2) in-package ~110um-thick optimized transformer with magnetic material (Bsat=0.77 T, coercivity=0.35 Oe, and resistivity>1e8 ohm∙cm). 166x boost in power per volume, 72%- delivery efficiency (14:1-ratio power Conv. + PDN) at 1 W/mm^2.

Reliability results obtained on a photosensitive polymer-based redistribution layer (RDL) process with two-metal layers and a target pitch below $4~\mu \text{m}$ are presented. Fully processed samples have been subjected to 1000 h of high-temperature storage (HTS) performed at 150 °C when a second set of samples endured a temperature–humidity (TH...

For die-to-wafer (D2W) stacking of high-density interconnects and fine-pitch microbumps, underfill serves to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, nonconductive film (NCF) has the advantages of fillet and volume control. However, one of the challenges is the solder joint wettin...

Three-dimensional (3D) complementary metal–oxide–semiconductor (CMOS) integration could enable device scaling beyond the limits of conventional 2D CMOS technology. Such integration requires vertical electrical connections that pass through silicon substrates and interconnect stacked chips. The fabrication of these through-silicon vias (TSVs) create...

We describe challenges of the epitaxial Si-cap/Si 0.75 Ge 0.25 //Si-substrate growth process, in view of its application in 3D device integration schemes using Si 0.75 Ge 0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si 0.75 Ge 0.25 with a thickness >10 ti...

The scaling of conventional solder-based flip chip bonding is facing its limitations due to thermal compression bonding overlay tolerance when using conventional bumping. To decrease the tolerance, planarization can be used to fabricate two flat surfaces for bonding. However, planarization of these soft and ductile surfaces is challenging by polish...

Silicon carbon nitride (SiCN) compounds have aroused great interest as dielectric materials for direct bonding because of the high thermal stability and high bond strength, as well as its Cu diffusion barrier properties. While wafer-to-wafer direct bonding, including the dielectric deposition step, is generally performed at high temperature (>350 °...

In this paper, we design, demonstrate and characterize a 3D printed package level polymer jet impingement cooling solution on a 23×23 mm 2 thermal test chip. The experimental hardware results for a nozzle pitch of 2 mm show that, with 1 kW power dissipation, at a coolant (DI water) flow rate of 3 liters per minute (LPM), the measured average chip t...