Christine Harendt

Institut für Mikroelektronik Stuttgart · Addon Processes

Plasma-enhanced atomic layer deposition (PEALD) is utilized to improve the barrier properties of an organic chip-film patch (CFP) when it is used as an implant to prevent moisture and ions from migrating into the embedded electronic circuits. For this purpose, surface condition and material properties of eight modifications of Al2O3-TiO2 nanolamina...

Hybrid Systems-in-Foil (HySiF) encompass large-area thin-film electronics and ultrathin, high performance CMOS chips, which are integrated into a flexible polymeric foil substrate. In this work, the individual components of a customized flexible sensor system are characterized in detail, i.e. , a strain gauge and a readout ASIC, and the system fu...

The characterization of multiple mechanically flexible passive and active electronic components, namely on-foil temperature sensor, relative humidity sensor, and ultra-thin microcontroller unit (MCU) integrated circuit (IC) is presented. These components are readily available for Hybrid System-in-Foil (HySiF) integration, which combines the merits...

Zur elektrischen Charakterisierung von organischen, speziell biologischen Materialien wurde ein CMOS ASIC mit aktiven Mikroelektroden entwickelt und gefertigt. Details dieses ASICs bezüglich Schaltungstechnik und Herstellverfahren werden präsentiert. https://www.mpc-gruppe.de/typo8/fileadmin/content/workshops-volums/MPC_Workshopband_61_62.pdf

This paper reports on the status of a comprehensive ten-year research and development effort towards Hybrid System-in-Foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier s...

Hybrid System-in-Foil exploits the complementary benefits of integrating embedded silicon chips with on-foil passive and active electronic components. In this work, the design, fabrication and characterization of three on-foil components, namely a humidity sensor, near field communication antenna and organic thin-film transistors, are investigated.

In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and a...

Nowadays, miniaturized digital image sensors are present in various applications ranging from consumer products such as camera phones to scientific and medical instruments. Because of the rapid reduction of structure size in semiconductor technology, small-sized image sensors have become feasible. Manufacturing of miniaturized cameras and the integ...

In this paper, a rigorous methodology for extracting the thermal compact model parameters of packaged chips is presented. The methodology is based on using a custom-designed test chip with multiple heating and temperature sensing elements in order to predict the temperature distribution in packaged chips after packaging. The technique involves meas...

The micro-hybrid system in foil (HySiF) involves ultra-thin chips embedded and interconnected in polymer foil for diverse flexible electronic applications. In this paper, the concepts and results of wafer level embedding and interconnection of ultra-thin dies in polymers are presented. The significant achievement of the presented HySiF is the accur...

Organic electronics have an enormous potential over a wide spectrum of promising low-cost and large-area applications, such as RFID tags, bio-sensors and flexible displays [1]. The organic thin-film transistor (OTFT) is an important building block for these novel applications. In fact, an OTFT-based circuit is integrated with other technologies (e....

Flexible circuit carriers with integrated ultra-thin silicon chips are the basis for a new generation of electronic systems. Highly complex silicon chips can now be manufactured very thin, with a thickness of a few micrometers and embedded in thin plastic films using the ECT-μVia (Embedded Component Technology) process. Other functions such as ante...

Implantable biosensors are key enablers for continuous diagnosis and monitoring of various disorders and the effects of drug intake on tissue and organs. The SMARTImplant consortium developed highly-integrated systems for in vivo biosensor applications [1]. The recent advancement of ultra-thin Application Specific Integrated Circuits (ASICs) fabric...

Abstract Ultra-thin silicon chips embedded inside flexible foils are envisioned to be the basis for an innovative generation of electronic systems. Highly complex silicon chips can be manufactured very thinly, mainly with a thickness of just a few microns and can be embedded in thin plastic films by the ECT-µVia process (Embedded Component Technolo...

Electronics embedded in foil is an enabling technology for flexible electronics and for special form factors of electronic components. In contrast to strictly printed electronics, Hybrid Systems-in-Foil (HySiF), comprising thin flexible, embedded chips and large-area thin-film electronic elements, feature a versatile and reliable technological solu...

Manufacturing ultra-thin chip is an emerging field in semiconductor technology that is driven by 3-D integrated circuits and flexible electronics. Unlike bulk silicon (Si) chips with thickness greater than 400 μm, the thermal management of ultra-thin Si chips with thickness smaller than 20 μm is challenging due to the increased lateral thermal resi...

The invention relates to an intracorporeal probe (10), for example preferably for examining hollow organs or natural or artificially created body cavities in the human or animal body, the probe (10) being designed in the form of a capsule that can be introduced into the body without external connecting elements, comprising an elongate housing (16)...

Ultra-thin silicon chips with thickness below 20 μm and excellent mechanical stability are embedded in a composite (benzocyclobutene and polyimide) foil substrate. Chemical vapor deposition (CVD) of Si3N4 on the silicon carrier substrate, on which that composite substrate is being processed, is proposed to compensate for the otherwise unavoidable w...

Various aspects of ultra-thin chip technology for flexible electronics are presented and discussed, including ultra-thin-chip fabrication, mechanical and electrical characterization, as well as chip assembly and imbedding. A stress sensor based on a stack of two ultra-thin, flexible CMOS chips indicates the particular advantages of the Chipfilm™ pr...

Here, we present a flexible sensor based on a stack of two ultra-thin IC-chips, exploiting the excellent chip thickness control in Chipfilm™ technology. The sensor consists of an almost stress-compensated bottom chip and a stress-sensitive top chip that are in good mechanical and thermal contact. Moreover, for the first time, we demonstrate that th...

In this paper, a novel two polymer composite (benzocyclobutene and polyimide) ultra-thin chip imbedding approach is demonstrated. Detailed processing steps including the formation of electrical interconnections by a conventional metallization process and pre-treatment of the substrate to facilitate the delamination of the embedded chip stack are di...

Various aspects of ultra-thin chip technology for flexible electronics based on Chipfilm™ technology are presented and discussed, including ultra-thin-chip fabrication, mechanical and electrical characterization, as well as chip assembly and imbedding.

Ultra-thin silicon (Si) chips fabricated using the recently developed Chipfilm™ technology feature three distinct manufacturing issues, which are discussed in this paper. In Chipfilm™ technology a thin Si membrane is firmly attached to a conventional bulk Si wafer by vertical Si micro-anchors which, however, in the end are controllably fractured to...

Here, we present a new concept for enabling the formation of TSVs in ultra-thin chips fabricated by using the ChipfilmTM technology. In this technology a buried cavity is created underneath a Si-membrane which is attached to the substrate by vertical silicon anchors. By applying thermal oxidation, the side walls of these anchors and the narrow cavi...

Active and passive electronic components are increasingly integrated within the printed circuit board itself. We are now on the threshold of a further development in which the PCB becomes more than a mere support for components. The printed circuit board is evolving to become ever more the central supporting element in solving construction problems...

A new concept for mechanically flexible stress and flex sensors is presented. A stack of two ultrathin chips is exploited to compensate both thermal effects and the vertical piezoresistive effect. By tailoring the thickness of the top die, the active devices of the bottom chip become stress compensated, whereas the devices of the top chip receive m...

The microsystem industry and market are diverse and are driven by small and medium size enterprises (SMEs), which call for a suitable technology foundry service. In the context of the German Excellence Cluster microTEC southwest three non-for-profit research and development institutes funded by the State of Baden-Wuerttemberg have joined forces to...

Flexibility of ultra-thin chips is an important condition for applications in flexible electronics. Especially, mechanical reliability of ultra-thin chips is a key factor generally determining the final performance and reliability of a flexible electronics product. Structures and designs implemented on the chips are the elements that weaken the mec...

The mechanical characteristics of ultra-thin silicon chips fabricated using Chipfilm™ technology are presented. Obtaining a chip thickness down to 8 μm ± 0.2 μm these chips are particularly capable for future system-in-foil applications [3]. Due to their small thickness mechanical stress resulting from CMOS process layers affects both the warpage a...

A novel method in minimizing mechanical bending stress on CMOS devices in ultra-thin chips is presented. It is shown, that the stress due to thin chip bending is reduced by glue-attaching a bare silicon chip on top of the active chip, thus shifting the neutral line to the active layer. The effect of the top chip thickness is investigated experiment...

Amorphous silicon based thin film photodiodes enhance the capabilities of optical detection in biosensing due to their high sensitivity, versatile adjustment of spectral response and ease of integration for point-of-care testing.

A new additive ultra-thin chip fabrication process is presented, utilizing an array of vertical anchors that mechanically connect silicon membrane chips to a standard silicon wafer. The process is demonstrated down to 8 μm silicon chip thickness, with a chip thickness control better than ±0.2 μm and a surface topography with average roughness <; 7...

In this chapter the recently introduced Chipfilm™ technology is presented. In contrast to subtractive wafer thinning techniques this technology is inherently additive, allowing for excellent control of extremely small chip thickness through epitaxial growth and for reuse of the wafer substrate. The thickness of the chips is essentially identical to...

Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the relat...

Modern medical diagnostics demands point-of-care testing (POCT) systems for quick tests in clinical or out-patient environments. This investigation combines the Reflectometric Interference Spectroscopy (RIfS) with thin film technology for a highly sensitive, direct optical and label-free detection of proteins, e.g. inflammation or cardiovascular ma...

Ultra-thin chip technology is identified as an enabler for overcoming bottlenecks in microelectronics, such as 3D integration, and for leading to new applications, such as hybrid, flexible system-in-foil (SiF). This, however, calls for new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in a...

Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the relat...

RF-ID-Systeme sind nicht mehr aus dem Alltag wegzudenken und werden in intelligenten drahtlosen Mikrosystemen eine immer wichtigere Rolle spielen. Mit Polymerelektronik können zwar kostengünstige RF-ID-Transponder, die in der Warenlogistik gefordert werden, hergestellt werden, aber komplexere Transponder für drahtlose Mikrosysteme mit integrierter...

Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips in such systems will provide solutions whenever high circuit performance and/or complexity are required. Ultra-thin Si chips (6 to 20 mum) are fabr...

Apart from the ongoing debate about using CMOS active pixel sensors (APS) or CCD imagers for today's consumer and commercial applications the emerging biomedical market presents new opportunities to CMOS APS. Logarithmic response high-dynamic range CMOS (HDRC) cells are the preferred photosensitive circuits for building sensors with contrast and no...

Christine Harendt heads the department Add-On Processes at the Institut für Mikroelektronik Stuttgart, Germany (IMS CHIPS). She is involved in the development and application of new technologies in combination with CMOS processes. In 1988, she received her Ph.D. in Physical Chemistry from Freie Universität, Berlin. The same year she joined IMS CHIP...

A 664 x 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips on foil will not only provide solutions whenever high circuit performance and/or complexity are required but also in a heterogeneous integration wi...

Presented is the design and characteristics of the first CMOS imager chip that has been implanted into a patient's eye with demonstration of partially-restored vision. Also presented and discussed are the design and characteristics of the first miniature APS imager chip based on thin-film-on-CMOS (TFC) photodiode technology targeted at low-cost and...

High dynamic range CMOS (HDRC ® ) imager technology, which is a special digital imaging concept suitable for a wide variety of applications, is reviewed in this paper. Important aspects of pixel cell layout and circuit/system design, based on which this CMOS imager concept is fully exploited, are discussed. Various applications of HDRC ® are illust...

High dynamic range CMOS (HDRCreg) imager technology is reviewed in this paper. Specific aspects of pixel cell layout and circuit/system design, based on which this CMOS imager concept is fully exploited, are highlighted. Various specific applications of HDRCreg are illustrated and future directions are indicated

The objective of the work in the EC project IVP is the development and evaluation of two prototypes of video systems:- a small wired videoprobe with a CMOS image sensorand- an autonomous video-capsule with a telemetric link for image data transfer to an external PC-based system.

The principles of the wafer fusion bonding technique at room temperature and with thermal treatment are described. Experiments using plain and patterned silicon wafers coated with different surface materials are presented. Results obtained for different thermal annealing conditions are discussed in terms of homogeneity and strength of the bond. Thi...

The basic principles of wafer fusion bonding including pretreatment, room temperature mating, and thermal annealing are presented. Techniques for the characterization of the bond quality are reviewed. Results for fusion bonding of other materials such as silicon nitride and polysilicon are discussed with a view to bond quality and application. Exam...

We present a novel sensor concept comprising a new contacting scheme for voltage-bias con- trolled thin film photodiode arrays on CMOS readout chips. Our unilateral contact structure greatly facilitates manufacturing of the sensor system. Moreover, the novel contacting scheme most efficiently suppresses crosstalk between neighboring pixels. The res...

Intelligent power ICs are increasingly desired for applications in automotive electronics, motor control devices or flat panel displays. In order to meet the requirements regarding reliability, low area consumption and flexibility the dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. In...

Burying SiO2 layers into silicon substrates by silicon direct bonding is one of the most promising substrate technologies for increasing the high-temperature capability of smart power devices for high-temperature applications. Leakage currents are suppressed and minority charge carriers are kept away from critical components. Temperature effects on...

Silicon direct bonding (SDB) has been used to produce silicon-on-insulator (SOI) substrates for dielectrically isolated power devices. The up-drain VDMOS transistors give a low specific on-resistance and allow multiple isolated outputs. The CMOS devices have down to 2 ¿m drawn channel lengths, here used in a channelless sea of gates semicustom arr...

Silicon on insulator on silicon (SOIS) has been produced with silicon direct bonding (SDB). Within a silicon film of 15-μm thickness, islands with ubiquitous oxide isolation have been formed for the simultaneous integration of 150-V power VDMOS transistors, CMOS circuits in a channelless sea-of-gates array with 2-μm gates, and bipolar transistors....

A novel LDMOS transistor structure with breakdown voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabrication by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1 μm. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, imp...

Thermal bonding of oxidized silicon wafers is used to obtain high-quality silicon on insulator (SOI) starting material for electronics and sensor applications. An overview of the technology is followed by a detailed description of the bonding technique and the ensuing wafer thinning processes for making SOI of various film thicknesses. Bonded pairs...

A limiting issue in the application of the BESOI (bond and etchback silicon-on-insulator) technique to whole wafers is the final film thickness nonuniformity, which typically totals approximately 40 nm using the etchback techniques presented to date. Such variation makes BESOI impractical for thin-film SOI (e.g. &les;300 nm) and applications to ful...

The quality of wafer-to-wafer bonds is investigated with regard to sensor applications. The two-step bonding process is described and experiments with different wafer surfaces are presented. Direct observation of the room-temperature bonding with infrared transmission allows the non-bonding areas to be detected and therefore the bonding process can...

Silicon direct bonding is a new technique offering a wide range of applications for sensor technology. Bonding of two oxidized wafers at room temperature and subsequent annealing is the basic process, which allows buried oxide layers to be fabricated. Additional doping or shallow epitaxial deposition permits the introduction of several etch-stop le...

Thermal bonding of oxidized wafers is used to produce dielectrically insulated silicon for device fabrication. The two step bonding process is described and experiments with different wafer surfaces including prestructured and nitride coated wafers are presented. Thinning techniques for Siliconon-Insulator (SOI) fabrication are compared regarding f...

In this paper a new ultra-thin chip fabrication and assembly process is presented. During a pre-process module Chipfilm™ wafer substrates are prepared with extremely narrow buried cavities. In contrast to the established wafer thinning technique, the overgrowth of porous silicon membranes using a standard silicon epitaxy process precisely defines t...

Abb. 1: Fotos von (a) ultradünnem und konventionel-lem Chip im Größenvergleich und (b) stark geboge-nem ultradünnem Chipfilm TM Chip. Abb. 2: Fotos von (a) 3-Punkt-Biegeapperatur für ult-radünne Chips und (b) Ausschnitt vom Biegespalt mit eingelegtem Chip, (c) Abbildung des Messprinzips. Kurzfassung Mit wachsenden Anforderungen an die Zuverlässigke...