![Illustration of the asymmetric double-edge PWM process, where the pulsed signal y[n] is determined by the intersection points of the amplitude signal a[n] with the triangular reference signal r[n]. Note that even though in a digital system the signals consist of discrete values, for a more comprehensible illustration the signals are drawn like continuous-time curves.](https://www.researchgate.net/profile/Christian-Vogel-7/publication/237065892/figure/fig1/AS:614021220806677@1523405475525/Illustration-of-the-asymmetric-double-edge-PWM-process-where-the-pulsed-signal-yn-is_Q320.jpg)
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1
Multiplierless Implementation of an Aliasing-Free
Digital Pulse-Width Modulator
Katharina Hausmair, Student Member, IEEE, Peter Singerl, Christian Vogel, Senior Member, IEEE
Abstract—Digital pulse-width modulators are used to trans-
form non-constant amplitude signals into pulsed signals, such
that the information lying in the signal amplitude is encoded in
the widths of pulses. Because of the inherent aliasing distortion in
digital pulse-width modulated signals, additional signal process-
ing steps are required to make pulse-width modulation (PWM)
suitable for applications like digital audio amplification or burst-
mode radio frequency (RF) transmitters. These processing steps,
however, entail an undesirable increase in computational effort.
This brief presents a multiplierless implementation of a digital
aliasing-free pulse-width modulator using look-up tables (LUTs),
adders and arithmetic shifts only. Mathematical equations of
asymmetric double-edge PWM are given, as well as a modi-
fied, aliasing-free version of this PWM technique that directly
integrates the distortion-avoiding signal processing steps into the
pulse-width modulator. Based on these equations, a multiplierless
implementation of the aliasing-free PWM is developed. Simula-
tion results obtained with a Simulink fixed-point model show
that the proposed modulator implementation provides a feasible
solution for realizing aliasing-free PWM with low computational
effort.
Index Terms—Aliasing-free digital pulse-width modulation
(PWM), switched-mode power amplifiers, burst-mode radio fre-
quency (RF) transmitters, computational effort
I. INT RO DU CTI ON
Digital pulse-width modulation (PWM) can be used to cre-
ate the switching signals for driving highly efficient switched-
mode power amplifiers (PAs), used in, e.g., digital audio
applications [1], or to generate the pulsed signals required in
burst-mode radio frequency (RF) transmitters [2]. For these
applications, a digital pulse-width modulator encodes a non-
constant amplitude input signal into a two-level pulsed signal
by encoding amplitude information into pulses of different
widths. The pulsed signal, or a passband equivalent of it, is
applied to the PA. After the PA, the amplified input signal, or
its passband equivalent, respectively, can be retrieved by using
Manuscript received XXXX, 20xx; revised Month, 20xx.
The research leading to these results has received funding from the
European Union’s Seventh Framework Programme (FP7/2007-2013) under
grant agreement n°248277. The Competence Center FTW Forschungszentrum
Telekommunikation Wien GmbH is funded within the program COMET -
Competence Centers for Excellent Technologies by BMVIT, BMWFJ, and
the City of Vienna. The COMET program is managed by the FFG.
Katharina Hausmair is now with the Department of Signals and Systems,
Chalmers University of Technology, SE-41296 G¨oteborg, Sweden (email:
hausmair@chalmers.se). This work was carried out while K. Hausmair was
affiliated with Graz University of Technology, Austria.
Peter Singerl is with Infineon Technologies Austria AG, Villach, Austria
(email: Peter.Singerl@infineon.com).
Christian Vogel is with the Telecommunications Research Center Vienna
(FTW), Austria (email: c.vogel@ieee.org).
Digital Object Identifier XXXXXXXX
an adequate filter. The high quality of the retrieved signal is
crucial for the aforementioned applications.
There are several well-established methods to encode a
non-constant amplitude signal into a pulsed signal, such as
Σ∆-modulation [3] or various comparator-based PWM meth-
ods [4]. All these methods, however, have in common that they
inherently suffer from distortion in and around the frequency
band of the input signal, which prevents retrieving a high
quality signal after amplification and the filtering operation [5],
[6]. Hence, a solution has to be found that eliminates the
distortion while maintaining low computational effort.
Several methods have been proposed to reduce or eliminate
the effects of the distortion. In [7], a noise cancellation circuit
that requires additional analog hardware is proposed. The
authors of [8] present an algorithm to optimize the noise
shaped coding performance of Σ∆-modulators. In [6], a Σ∆-
modulator comprising noise shaping loop-filters in combina-
tion with a digital feedforward error correction method is
introduced. This concept is further elaborated in [9]. In [5], the
authors introduce a modified version of asymmetric double-
edge PWM that eliminates all destructive aliasing distortion
but requires a large number of multiplications and trigono-
metric functions, which increases the computational effort
compared to a comparator.
In this brief we show that the method proposed in [5] can
be implemented by using look-up tables (LUTs), adders and
arithmetic shifts only. The suggested implementation therefore
allows for generating practically distortion-free digital pulse-
width modulated signals in a computationally efficient way.
II. AS Y MM ETR IC DO UBL E-EDGE PWM
A digital pulse-width modulator transforms the amplitude
signal a[n]∈[0,1] into a train of two-level pulses y[n]
of different widths at a fixed pulse period Tp. Hence, the
information lying in the amplitude of a[n]is encoded in the
widths of the pulses of y[n]. A common PWM method is
asymmetric double-edge PWM [4], where the pulse train y[n]
consists of asymmetrical pulses that are centered around the
midpoint of the pulse period Tp. The edges of the pulses,
i.e. the transitions between the two levels 0and 1, can be
determined by finding the intersection points of the amplitude
signal a[n]with a triangular reference wave r[n]that is
periodic in Tp. This process is depicted in Fig. 1.
Note that for the PWM method described here, the am-
plitude signal a[n]has to fulfill certain constraints. First, the
bandwidth of a[n]must be adequately smaller than the refer-
ence wave frequency fp= 1/Tp[10]. Second, the amplitudes
Copyright ©(c) 2013 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained
from the IEEE by sending an email to pubs-permissions@ieee.org.
2
1
n
Tp
Ts2Tp
Ts3Tp
Ts
a[n]
r[n]
y[n]
Fig. 1. Illustration of the asymmetric double-edge PWM process, where the
pulsed signal y[n]is determined by the intersection points of the amplitude
signal a[n]with the triangular reference signal r[n]. Note that even though in a
digital system the signals consist of discrete values, for a more comprehensible
illustration the signals are drawn like continuous-time curves.
of a[n]have to lie within the interval [0,1] [5]. In order to use
the described asymmetric double-edge PWM for signals that
do not meet the latter requirement, appropriate preprocessing
steps have to be applied. For a real-valued signal, proper
scaling and adding a bias could solve the problem. For a
complex-valued signal, a polar system architecture or an IQ-
system architecture can be implemented [11]. In a polar
architecture, PWM is performed on the magnitudes of the
signal and phase modulation is performed subsequently [5]. In
an IQ-architecture, PWM is performed on real and imaginary
parts of the signal separately, requiring a signal combiner
afterwards.
The asymmetric double-edge PWM operator P(a[n], r[n])
is [5]
P(a[n], r[n])= 1,for a[n]≥r[n]
0,for a[n]< r[n](1)
and the pulse-width modulated signal y[n]is given by [5]
y[n]= a[n] +
∞
X
k=1
2(−1)k
πk sin (πka[n]) cos 2πk Ts
Tp
n(2)
where Tsis the system clock period.
Conventional digital asymmetric double-edge PWM can be
implemented with low computational effort by using a com-
parator. However, as has been shown in [5], the nonlinear non-
bandlimited operation of the pulse-width modulator inevitably
induces aliasing in the resulting pulsed signal y[n]. The
aliasing effect causes distortion in and around the frequency
band of the amplitude signal a[n]. Hence, when recovering the
amplitude signal a[n]from the pulsed signal y[n], distortion
remains within the recovered signal. Due to the aliasing effect,
conventional PWM is not suitable for applications where the
amplitude signal a[n]has to be recovered with high quality
from the pulsed signal y[n][5], [12], e.g. in burst-mode
RF transmitters or digital audio applications. Therefore, the
authors of [5] developed an aliasing-free PWM method, where
aliasing is completely avoided.
III. ALI AS ING -F REE PWM
The aliasing-free PWM method is based on the conventional
comparator PWM described in Sec. II. To avoid the aliasing
effect, the PWM operator P(a[n], r[n]) is slightly altered in a
way that limits the frequency content of the pulsed signal y[n],
which is then given by [5]
y[n]= a[n] +
K
X
k=1
2(−1)k
πk sin (πka[n]) cos 2πk Ts
Tp
n(3)
where Kis a finite number that ensures that the frequency
content of the pulse-width modulator output y[n]is limited
to an amount that avoids destructive aliasing in and around
the frequency band of the amplitude signal a[n]. As a con-
sequence, the aliasing-free PWM cannot be implemented by
a comparator. Instead, the pulsed signal y[n]is obtained
by computing (3). In order to do so, a large number of
multiplications and sine and cosine computations is required,
where the computational effort increases with the number of
harmonics K. These operations might be costly when using
fixed-point hardware such as ASICs and FPGAs [13], and
they make a straightforward implementation of the aliasing-
free PWM in hardware expensive compared to a comparator.
Hence, an implementation with low computational effort is
required in order to make the aliasing-free PWM a viable
candidate for practical applications. Our work therefore aims
at developing an implementation of the aliasing-free PWM
that does not require computationally expensive operations like
multiplications and trigonometric functions.
IV. IMP L EM ENTATI ON
In order to avoid multiplications and trigonometric func-
tions, the use of look-up tables (LUTs) is targeted as an
alternative. To obtain such a solution, (3) is rewritten as
y[n] =a[n]+
K
X
k=1
(−1)k
πk sin 2πk Ts
Tp
n+πka [n]
−sin 2πk Ts
Tp
n−πka [n]!.(4)
By exploiting the 2π-periodicity of sine waves, (4) can be
written as y[n] = a[n] + y1[n]−y2[n], where
y1[n]=
K
X
k=1
(−1)k
πk sin 2πk β[n] + a[n]
2
y2[n]=
K
X
k=1
(−1)k
πk sin 2πk β[n]−a[n]
2 (5)
and
β[n]= mod Ts
Tp
n, 1(6)
is introduced to facilitate a convenient hardware realization.
From the above equations, it can be seen that for a specific
amplitude a[n]both terms y1[n]and y2[n]approximate inverse
Tp-periodic sawtooth waves, where different values of a[n]
merely induce different phase shifts, without changing the
shapes of the waves at all. This is illustrated in Fig. 2, where
the sawtooth waves for K= 10 are depicted for two examples
of a[n].
3
y1[n]|a[n]=0
y2[n]|a[n]=0
−0.5
0.5
0Tp
2
Tp
Amplitude
(a) The sawtooth waves for a[n] = 0.
y1[n]|a[n]=0.5
y2[n]|a[n]=0.5
−0.5
0.5
0Tp
2
Tp
Amplitude
(b) The sawtooth waves for a[n] = 0.5.
Fig. 2. Illustration of one period Tpof the sawtooth waves y1[n]and y2[n]using K= 10 for different amplitude signals a[n], resulting in different time
shifts.
β[n]
NFP
a[n]
NFP >>1
NFP
+
+
−
+
NLUT
NLUT
<<NLU T
<<NLU T
i1[n]
i2[n]
NLUT
NLUT LUT1
y1[n]
NFP
LUT2
y2[n]
NFP +
−
+
y[n]
NFP
Fig. 3. Block diagram of the implementation assuming modular arithmetic, where also the fixed-point word lengths are indicated.
In order to implement the PWM with LUTs, we propose to
compute the LUT entries yLU T [i]as
yLUT [i]=
K
X
k=1
(−1)k
πk sin 2πk i
2NLUT (7)
where 2NLUT is the number of values stored in the LUT and
the index i= 0,...,2NLU T −1. Hence, an LUT comprises
values for one complete sawtooth period.
To obtain y1[n]and y2[n]from the LUTs, the indices i1[n]
and i2[n]for the amplitude signal a[n]at the current time
index nneed to be computed as
i1[n]= jmod β[n] + a[n]
2,12NLUT k
i2[n]= jmod β[n]−a[n]
2,12NLUT k(8)
where the number representation of i1[n]and i2[n]has to be
consistent with the representation of i.
Finally, the aliasing-free pulse-width modulator output can
then be computed by
y[n] = a[n] + yLU T [i1[n]] −yLUT [i2[n]] .(9)
In hardware, the multiplications by 1/2Nand 2Ncan be
completely avoided by implementing them as arithmetic shift
operations, denoted by (x >> N)∧
=x/2Nand (x << N )∧
=
x2N.
Furthermore, due to periodicity, β[n]can be implemented
as a periodic counter with step size Ts/Tp, running within the
interval [0,1).
Fig. 3 depicts the block diagram of the implementation.
The modulo-operations in the above equations can be enforced
by using modular arithmetic, which automatically ensures that
numbers “wrap around” after they reach a certain value. By
implementing the aliasing-free PWM method according to the
block diagram in Fig. 3, the computational effort becomes in-
dependent of the number of harmonics K. The computational
effort can be reduced, since there are no multiplications or
trigonometric functions required. Table I compares the number
of required calculations for the multipliereless implementation
to a straightforward implementation of (3). It can be seen that
for the straightforward implementation the number of multipli-
cations as well as sine and cosine computations increases with
the number of harmonics K, while the proposed implemen-
tation does not require any multiplications or sine and cosine
computations at all. However, the proposed implementation
requires the use of at least two LUTs. The number of entries
2NLUT in the LUTs determines the accuracy of the output
signal y[n]. This is investigated in Sec. V.
Note that the proposed modulator implementation can also
be used to implement the conventional two-level asymmetric
double edge PWM given in (2). This can be done by using a
perfect sawtooth wave for yLU T [i], instead of an approxima-
tion.
4
TABLE I
CAL CU LATIO NS R EQUI RED F OR S TRAI GHT FO RWAR D AN D
MU LTI PLI ERLE SS IM PLEM ENTATI ON S OF T HE A LIA SI NG-FR EE PWM I N
MATLA B SIM U LI NK .
straightforward
implementation
according to (3)
proposed
implementation
Multiplications 4K0
Sine/Cosine 2K0
Arithmetic shifts 0 3
Sums K4
x[n]
|x[n]|
a[n]
PWM
y[n]
∠x[n]
φ[n]
ejφ[n]
yφ[n]
Fig. 4. Block diagram of PWM in a polar architecture.
V. SI MUL ATI ON RE SULTS
For the evaluation of the proposed PWM implementation,
a complex-valued baseband signal x[n]is used, where x[n] =
a[n]ejφ[n]. The PWM was implemented in a polar system ar-
chitecture, like for example in [5], [6]. In such an architecture,
PWM is performed on the magnitude signal a[n] = |x[n]|,
and phase modulation of the pulsed signal y[n]is performed
subsequently to obtain the signal yφ[n] = y[n]ejφ[n]. A block
diagram of a polar PWM architecture is depicted in Fig. 4. For
such an architecture, the signal y[n]is used for time domain
evaluation, while the phase modulated signal yφ[n]is used for
frequency domain evaluation [5].
The multiplierless implementation described in Sec. IV has
been modeled in the Matlab Simulink fixed-point environment.
In order to present an application independent evaluation, for
the interpretation of the results ratios of the parameters Ts,Tp
and the bandwidth Bxof the input signal x[n]are given rather
than absolute values. Following the recommendations in [5],
the settings for these parameters for all presented simulation
results are chosen as Tp/Ts= 14,1/(TpBx) = 7. The fixed-
point word length is denoted as NF P .
A. Time Domain Evaluation
In order to show that the proposed implementation works
properly, simulations have been conducted where the pro-
posed implementation is configured to emulate the comparator
PWM. This can be done by using a perfect sawtooth wave
for yLU T [i], i.e., K=∞, instead of an approximation.
The obtained results are compared to results obtained by a
fixed-point Simulink model of the conventional comparator
PWM. The LUT settings and the fixed-point word length are
NLUT =NF P = 16. Fig. 5 shows a representative example
of pulsed signals y[n]generated with both modulators for the
same amplitude signal a[n]. It can be seen that the results are
identical, which verifies the correct operation of the proposed
implementation.
Pulsed Signa l y[n]
LUT Output y1[n]
LUT Output −y2[n]
Amplit ude Sig nal a[n]
Amplitude
Sample Number n
0
0 20 40 60 80 100
−0.5
−0.25
0.25
0.5
0.75
1
(a) Proposed PWM implementation.
Pulsed Signa l y[n]
Ref ere nce Wave r[n]
Amplit ude Sig nal a[n]
Amplitude
Sample Number n
0
0 20 40 60 80 100
0.25
0.5
0.75
1
(b) Comparator PWM.
Fig. 5. Comparison of simulation results obtained with Simulink fixed-point
models of 5(a) the proposed implementation emulating conventional PWM,
and 5(b) conventional comparator PWM. The resulting pulsed signals y[n]
are identical.
B. Frequency Domain Evaluation
For applications like digital audio and RF transmitters,
the amplified input signal x[n]or a passband equivalent
has to be recovered from the amplified pulsed signal by a
filter [5]. In order to achieve high quality of the recovered
signal while ensuring feasibility of the filtering operation, it
is important that the distortion that is caused by the PWM
process in and around the input signal frequency band is
kept low. The dynamic range (DR) serves as a measure of
the amount of distortion introduced in the frequency band of
interest. It is defined as the difference between the average
power of the desired signal and the power of the surrounding
distortion given in dB. To evaluate the performance, the DR
for frequency bands adjacent to the band of x[n]was used,
i.e. for frequencies fadj ∈(Bx/2,2Bx].
It has been shown in [5] that the aliasing-free PWM is
practically free of distortion in the frequency band of interest
and hence outperforms the comparator-based PWM in terms
of DR. However, when generating the pulsed signal y[n]
with the proposed implementation in fixed-point arithmetic,
amplitude quantization error is introduced. This error is due
to the finite word length NF P of the fixed-point numbers
and due to the finite number 2NLUT of values stored in the
LUTs. The amplitude quantization error decreases the DR. The
effects of amplitude quantization on the proposed aliasing-free
PWM implementation are shown in Fig. 6. The figure shows
examples of power spectral densities (PSDs) of aliasing-free
phase modulated pulsed signals yφ[n]with K= 5, obtained
5
8bit C-PWM
8bit AF-PWM
10bit AF-PWM
12bit AF-PWM
14bit AF-PWM
16bit AF-PWM
Input Signal
PSD in dB/Hz
Frequency
−3fp−2fp−fpfp2fp3fp
0
0
−20
−40
−60
−80
−100
Fig. 6. PSDs of pulsed signals yφ[n]generated with comparator PWM (C-
PWM), and the model of the proposed aliasing-free PWM implementation
(AF-PWM) for different NLUT =NF P . The PSD of the unquantized input
signal x[n]is also shown.
for simulations with different fixed-point word lengths NF P
and LUT entries 2NLU T , where NLU T =NF P . The figure also
shows the result of the comparator PWM for NF P = 8, as well
as the unquantized input signal x[n]. Comparing the results
of the aliasing-free PWM to the comparator-based PWM, it
can be seen that even for NLU T =NF P = 8, the aliasing-
free PWM outperforms the comparator-based PWM in terms
of DR. By using NLU T =NF P = 16, the proposed imple-
mentation of the aliasing-free PWM achieves a DR of around
89 dB, which is an improvement of around 60 dB compared
to the comparator-based PWM implementation, which reaches
a DR of only 29 dB. Hence, even for fixed-point arithmetic
of short word lengths the superior spectral properties of the
aliasing-free PWM persist.
Note that the DR of the comparator PWM does not increase
for NF P >8. This indicates that the distortion caused by
aliasing outweighs the amplitude quantization error for the
comparator PWM.
C. Considerations on Further Effort Reduction
The fixed-point word length NF P and the LUT resolution
NLUT are independent and can therefore be chosen differently.
Table II shows the DRs of simulations with different NF P and
NLUT . From the results it can be concluded that the lower
bound of the DR is determined by the fixed-point word length
NF P , i.e., for a fixed NF P no improvement can be achieved by
choosing NLU T > NF P . However, for a fixed number of LUT
entries 2NLUT , the resulting DR can be improved significantly
by using fixed-point operations with NF P > NLU T . Hence, by
carefully investigating the system requirements while taking
into account the input signal characteristics, the computational
effort of the aliasing-free PWM can be further reduced.
Note that the fixed-point word length NF P does not have
to be the same for all signals throughout the implementation.
Hence, the computational effort could possibly be further
improved by optimizing the fixed-point word length NF P and
the number of LUT entries 2NLUT that is required to obtain the
desired quality of results. However, the purpose of this brief is
to present the idea behind the implementation algorithm rather
than to optimize it in every possible aspect.
TABLE II
DR S IN D BF OR A LI AS I NG -FR EE PWM F OR DI FFE RE NT NLU T AND NF P .
PPPPP
P
NF P
NLUT 8 10 12 14 16
8 44 44 44 44 44
10 52 53 53 53 53
12 55 66 67 67 67
14 55 67 77 81 81
16 55 67 79 89 89
VI. CO NCL US ION S
A multiplierless implementation of digital PWM has been
presented that is based on the aliasing-free PWM method
in [5]. For the implementation, LUTs and arithmetic shift oper-
ations are utilized in a way that allows for completely avoiding
computationally expensive multiplications and trigonometric
functions. Simulations demonstrate that the proposed im-
plementation of the aliasing-free PWM provides a simple
technique with only low computational effort to implement
high DR digital PWM, which makes it suitable for applications
employing switched PAs, such as digital audio or burst-mode
RF transmitters.
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