Content uploaded by Chi On Chui
Author content
All content in this area was uploaded by Chi On Chui on Mar 03, 2014
Content may be subject to copyright.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 1817
Synthesized Compact Models and Experimental
Verifications for Substrate Noise Coupling
in Mixed-Signal ICs
Hai Lan, Student Member, IEEE, Tze Wee Chen, Student Member, IEEE, Chi On Chui, Member, IEEE,
Parastoo Nikaeen, Student Member, IEEE, Jae Wook Kim, Student Member, IEEE, and
Robert W. Dutton, Fellow, IEEE
Abstract—A synthesized compact modeling (SCM) approach for
substrate coupling analysis is presented. The SCM is formulated
using a scalable
matrix approach for heavily doped substrates
with a lightly doped epitaxial layer and using a nodal lumped resis-
tance approach for lightly doped substrates. The SCM models re-
quire a set of process-dependent fitting coefficients and incorporate
geometrical parameters of the substrate ports in a compact form
that includes size, perimeter, and separation defined using the geo-
metric mean distance to accommodate both far-field and near-field
effects. The SCM approach is verified based on measurement data
from two test chips, one in a custom lightly doped process and the
other one using a 0.18-
m BiCMOS lightly doped foundry process.
The model accuracy is shown to be within 15% compared to mea-
sured data extracted from the test patterns. The SCM is exploited
with application examples to show substrate model generation ef-
ficiency and accuracy at different levels of complexity, including a
full chip substrate noise distribution analysis for a 2 mm by 2 mm
chip with 319 substrate contacts.
Index Terms—Compact model, mixed-signal circuits, substrate
noise.
I. INTRODUCTION
M
IXED-SIGNAL IC design and system-on-chip (SOC) in-
tegration has continued to be challenged by substrate
noise coupling issues. Due to the semi conductive nature of the
substrate, switching activity of digital circuits inevitably gen-
erates undesired current noise. This noise is injected into and
propagates through the substrate to degrade the performance of
sensitive analog or RF circuits residing on a common substrate.
Fig. 1 illustrates an overview of substrate noise coupling phe-
nomena in a typical mixed-signal circuit, including substrate
noise generation, propagation and coupling processes. There are
three major noise injection mechanisms, as labeled in Fig. 1,
including impact ionization due to hot electron effects, capac-
itive coupling through reverse biased source/drain-bulk junc-
tion capacitance, and supply noise at power and ground con-
tacts mainly due to inductive
noise, which are labeled
Manuscript received October 31, 2005; revised March 24, 2006. This work
was supported by the Defense Advanced Research Projects Agency (DARPA)
under the NeoCAD project.
H. Lan, T. W. Chen, P. Nikaeen, J. W. Kim, and R. W. Dutton are with the De-
partment of Electrical Engineering and Center for Integrated Systems, Stanford
University, Stanford, CA 94305 USA (e-mail: hailan@gloworm.stanford.edu).
C. O. Chui is with Intel Corporation, Santa Clara, CA 95052 USA.
Digital Object Identifier 10.1109/JSSC.2006.877272
Fig. 1. Illustration of substrate noise generation, propagation, and coupling
processes in mixed-signal circuits. Three major noise generation mechanisms
are labeled as: 1–impact ionization; 2–capacitive coupling; and 3–power supply
bounce.
in Fig. 1. As technology scaling advances, impact ionization be-
comes negligible and source/drain junction capacitive coupling
becomes less pronounced compared to supply noise at the power
and ground contacts [1]. This will remain so in the future tech-
nology nodes.
Proper substrate modeling is required to include the substrate
noise coupling effects in the design process. Considerable
research efforts have been invested in characterizing and mod-
eling the substrate. There are two major schools of methodology
for modeling the substrate, mesh-based approaches and com-
pact macro models. The first approach relies on fine 3-D grid
meshing schemes to discretize the entire substrate and/or
the substrate ports in order to solve the Poisson and conti-
nuity equations, quasi-static Laplace equations, or full-wave
Maxwell equations. Many mesh-based numerical extraction
methods using finite difference method (FDM), finite element
method (FEM), or boundary element method (BEM) have been
reported [2]–[7]. While accurate, they are computationally
expensive and thus usually limited to simple configurations.
The second method seeks to develop macro models in scalable
and compact form. The latter approach has the advantage in fast
generation of substrate models which can enable practical and
efficient large scale substrate port extraction. Such modeling
method for heavily doped substrates has been proposed in [8]
and [9]. Lightly doped substrates are widely used in today’s
mixed-signal technology. The high resistivity of substrates
provides better noise isolation and suppresses eddy currents
in the substrate, thus making it possible to integrate high
0018-9200/$20.00 © 2006 IEEE
1818 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
quality passive components. There have been various analysis
and experimental characterization reported for lightly doped
substrates, e.g., [10] and [11]. A recent work in [12] proposed
a surface potential-based model for layered lightly doped sub-
strates. This macro model, however, requires discretization of
rectangular contacts into circular meshes and a few empirical
parameters, which are partially geometry-dependent. A more
attracted macro modeling approach should be truly scalable
with layout geometry without requiring meshing, with a limited
set of process-dependent fitting coefficients for a given process.
Hence, it is desirable to formulate and develop a modeling
methodology which allows efficient substrate network gener-
ation for noise analysis and provides scalability with layout
geometries, thereby providing insightful information that can
be used to reduce re-layout efforts and facilitate noise-aware
layout synthesis. Synthesized compact modeling (SCM) for
substrate noise coupling, that addresses the above modeling
challenges, will be introduced in this paper. Moreover, the sub-
strate can be treated as purely resistive for frequencies below
1–2 GHz for heavily doped processes and for frequencies below
about 10 GHz for lightly doped processes [13]. Substrate noise
sources have wide frequency spectra but the major components
are typically within the frequency range mentioned above.
The digital noise profile can be characterized using macro
modeling method, e.g., [14]. Hence, this paper will focus on
the development of resistive substrate network.
This paper is organized as follows. In Section II, the required
modeling parameters are discussed, followed by a review of the
implication of the near-field and far-field effects in the substrate
noise coupling context; the SCM formulation is then presented
for heavily doped substrates and lightly doped substrates, re-
spectively. Section III details the comparison between the mod-
eling results and measurements from two test chips. Section IV
discusses the application of the SCM models with examples at
different levels of complexity. Finally, the conclusions are pre-
sented in Section V.
II. SCM A
PPROACH
A. Modeling Parameters
The development and formulation of synthesized compact
models (SCM) requires two types of modeling parameters,
namely, technology process related parameters and layout
geometry related parameters.
The first parameter set is normally determined from the
process-dependent substrate doping profile, which in turn is
usually given as the spreading resistance profile (SRP) data.
This data is applied as an input to 3-D technology CAD
(TCAD) or electromagnetics (EM) simulations. It is this infor-
mation that determines the fitting coefficients in the analytical
expressions of the SCM. In modern IC technologies, there are
two major types of substrate, i.e., heavily doped substrates with
a lightly doped epitaxial layer and lightly doped substrates. In
both cases, the substrate can be well approximated as a strat-
ified structure with layers of uniform resistivities. Typically,
a heavily doped substrate with lightly doped epitaxial layer
can be well approximated by a three-layered structure [15].
A lightly doped substrate can be approximated by a three-
to six-layered structure with sufficient accuracy [16]. This
allows great reduction in the TCAD simulation cost and model
development efforts.
The second set of parameters refers to the geometrical param-
eters of the substrate coupling ports, including shape, size, area,
perimeter and separation, based on the circuit layout. It is these
geometrical parameters that gives the scalability of the SCM
thereby allowing efficient model generation and noise-aware
layout optimization. A substrate port should be physically de-
fined at the circuit layout level. The definition usually involves
the union set of several physical mask layers according to the
specific process-dependent technology file. The ports defined
are normally rectangular in shape, which are fully described by
the corner coordinates. Therefore, several geometrical proper-
ties associated with each port and each of a pair of ports are of
particular importance. They are port area
, perimeter , and
separation
between two ports. Although the first two pa-
rameters are self explanatory, the so called separation
is not
defined clearly and it should be revisited as follows.
A scalable model parameterization requires a proper defini-
tion of separation, spacing, or distance. Edge to edge distance is
often used when two contacts are well aligned and this regular
definition of separation is clear. However, this is not applicable
in general. When two contacts are not aligned and are not far
away from each other, the regular definition of separation be-
comes ambiguous. In reality most contacts are arbitrarily posi-
tioned in a layout. Hence, a more appropriate and generic defi-
nition of separation needs to be introduced so that this geomet-
rical parameter can be included in the compact model without
any ambiguity. For this purpose, the concept of geometric mean
distance (GMD) is introduced here as a metric of the separa-
tion between two substrate ports. Fig. 2 illustrates a generalized
configuration of two rectangular contacts arbitrarily positioned.
The GMD,
,isdefined as following:
(1)
where r is the distance between points
and ,
and are the widths of two contacts, and are the lengths
of two contacts. By definition, it takes into account the area,
perimeter, and relative position of two contacts. Since the rig-
orous definition in (1) involves a multiple integral computation,
it is desirable to approximate it using less complicated forms.
For certain configurations, the formula given by (1) can actu-
ally be further simplified to create a compact, closed-form set
of expressions [17].
B. Near-Field and Far-Field Effects
Although it is widely believed and generally true that the sub-
strate coupling between two substrate ports decreases when the
separation increases, the subtleties of the difference in near-field
region and far-field region behavior have been less well rec-
ognized. Depending approximately on the relative aspect ratio
of the size of the two ports and their separation between them,
the coupling decay trend behaves differently in the two regions.
This can be explained both geometrically and physically. From
the layout geometry point of view, when the separation is large
LAN et al.: SYNTHESIZED COMPACT MODELS AND EXPERIMENTAL VERIFICATIONS FOR SUBSTRATE NOISE COUPLING IN MIXED-SIGNAL ICs 1819
Fig. 2. Illustration of using geometric mean distance (GMD) to define the sep-
aration.
enough compared to the contact size, both contacts see each
other simply as lumped points. By contrast when the two con-
tacts are close to each other, the spreading effects of the current
flow are more significant. Hence, the shape, size, alignment and
relative position all contribute to the overall coupling strength.
From the device and electromagnetic physics points of view, in
the near-field region the magnitude of the electric field drops off
at a rate proportional to
whereas in the far-field region it
drops off at a much slower rate proportional to
[18]. More-
over, in the area close to the contact, the equal potential lines are
spaced closely, implying a rapidly dropping voltage and there-
fore a greater current density in that region. Hence, when the
separation is relatively large, the near-field effect dominates in
the area close to the noise aggressor and victim and the far-field
effect dominates along most of the long range coupling path;
when the separation is small, the near-field effect dominates.
As a result, when the separation is small the coupling strength
is stronger than what is predicted by simple models suitable for
far-field coupling, e.g., [9]; when the separation is large the cou-
pling strength approaches a saturated level as opposed to the
first-order model that predicts it decays significantly with in-
creasing distance.
C. Heavily Doped Substrate
Fig. 3 illustrates the cross section of a heavily doped sub-
strate with lightly doped, epitaxial layer on top. As illustrated
in the figure, a heavily doped process features a heavily doped,
thick bulk substrate with a very low resistivity in the order of
cm, and a lightly doped, thin epitaxial layer with
a high resistivity in the order of
cm. Therefore,
the entire bulk substrate can be treated as a single, lumped node
from the equivalent circuit modeling point of view. Moreover,
the back plane of the bulk substrate is typically grounded. There-
fore, the bulk substrate grounded through the back plane is the
common ground to all the substrate coupling ports from the net-
work point of view. The SCM approach exploits these charac-
teristics to formulate the substrate coupling using a
matrix
method, where the self impedance term and mutual coupling
impedance term are separately modeled.
For a multiple contact configuration, which represents most
situations in practical circuit layouts, multi-port
matrix-based
models can reasonably predict the overall interaction between
Fig. 3. Cross section of a typical heavily doped substrate with a lightly doped
epitaxial layer.
any two contacts in the presence of all other nearby contacts.
In general for an
contact configuration, the corresponding
matrix characterizing the overall coupling between all the
contacts is
.
.
.
.
.
.
.
.
.
(2)
where all the self and mutual impedance terms in the
matrix
have been modeled using the geometry-dependent analytical ex-
pressions in [9] for a heavily doped process with a lightly doped
epitaxial layer. The
term can be modeled by the following
analytical expression:
(3)
where
, and are fitting parameters, which are only
process-dependent. The
term is also modeled in [9]. While
it is suitable for the far-filed region, it underestimates the
substrate coupling strength due to more spreading effects in
the near-field region. As the separation increases, the coupling
decays in an exponential fashion in the far-field region and falls
off more rapidly than exponentially in the near-field region. A
complete model of
is proposed here to account for both
near-field and far-field effects to improve the model in [9] in
the near-field region:
far-field
near-field
(4)
where
, , and are process-dependent fitting parameters.
, , and can be derived using the self impedance for-
mula in (3). Fig. 4 shows the comparison of
between the
comprehensive SCM model, simple extension of far-field model
and 3-D device simulation results using Davinci [19]. While the
pure far-field model predicts the mutual coupling strength well
in the far-field region, it deviates from the reference data from
the device simulation when simply extended into the near-field
region. Although not clearly defined, the transition point be-
tween the near-field and far-field is roughly at where the separa-
tion is the same as the contact size. The reference data suggests
that the direct extension of the far-field model into the near-field
region leads to an underestimation of the coupling strength by
1820 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
Fig. 4. Mutual impedance in near-field and far-field region. Simple exten-
sion of far-field model into near-field region results in large deviation from the
reference device simulation data.
Fig. 5. Cross section of a typical lightly doped substrate.
a factor of as much as 300% for this particular case. The newly
proposed comprehensive model agrees with Davinci simulation
results in both the near-field and far-field regions.
D. Lightly Doped Substrate
Fig. 5 depicts the cross section of a lightly doped substrate,
which is widely used in analog, RF and mixed-signal circuits.
The less lossy substrate enables high performance passive com-
ponents, such as on-chip spiral inductors. Eddy currents are
more difficult to excite in the silicon bulk. This configuration
also favors better substrate noise isolation. As illustrated in
Fig. 5, a lightly doped substrate mainly features a lightly doped
bulk substrate with a relatively high resistivity in the order
of 10
cm. The nature of this high resistivity bulk substrate
determines that the bulk part can not be treated as a single,
lumped node for the equivalent substrate network. The proper
biasing of the substrate relies on the deployment of many p+
substrate contacts on the surface. Unlike the case in the heavily
doped processes, for the lightly doped substrate processes
there is no common ground to all the substrate coupling ports
from the network point of view. Therefore, a resistance-based
formulation is used to develop the SCM model for lightly doped
substrate processes.
In the lightly doped substrates, the near-field effect still ex-
ists but exhibits its influence in a slightly different way. For the
far-field configuration the current injected into the substrate by
the noise aggressor tends to penetrate more deeply in the vertical
direction before it is sensed by the victim while for a near-field
configuration it tends to crowd to the surface region along the
direct path between two contacts. As a consequence, when the
separation increases, the coupling first experiences a decay in
an almost exponential fashion in the near-field region. However,
the coupling will not decay indefinitely to zero as the separation
further increases into the far-field region. Instead, the coupling
tends to approach a saturation level. Hence, the proposed com-
pact model of substrate coupling resistance between two arbi-
trarily sized contacts can be expressed as
(5)
where
is the GMD between the two contacts; and are
the areas of contact
and contact , respectively; and and
are the perimeters of contact and contact . The terms ,
, , and are four fitting coefficients, characterizing the
substrate coupling resistance’s dependence on substrate doping
profiles, separation between two contacts, contact areas, and
contact perimeters, respectively. These fitting parameters are in-
dependent of layout geometry but are only process-dependent.
E. Equivalent Circuit Model of Substrate Coupling Network
It should be emphasized that the resistance-based network
can be converted to the equivalent impedance-based network.
In general for an
-contact configuration the substrate coupling
network can be in the form of a resistance
matrix:
.
.
.
.
.
.
.
.
.
(6)
or an impedance
matrix:
.
.
.
.
.
.
.
.
.
(7)
The
matrix is more convenient to use when a direct equiv-
alent circuit model is preferred, for example, the inclusion of
a substrate netlist as a subcircuit for circuit level SPICE sim-
ulation. The
matrix, however, is more advantageous when a
network-based analysis is of interest, for instance, the imple-
mentation of the macro model for behavioral level simulation.
Each term in the
matrix is a complicated, if not difficult to
understand conceptually, function of many resistances. Fig. 6
shows a two port configuration example. In this configuration,
between two substrate ports there is a cross coupling resistance,
, and resistances and from each of the ports to the
LAN et al.: SYNTHESIZED COMPACT MODELS AND EXPERIMENTAL VERIFICATIONS FOR SUBSTRATE NOISE COUPLING IN MIXED-SIGNAL ICs 1821
Fig. 6. Resistance and impedance network for the substrate coupling between
two ports.
Fig. 7. Cross sectional view of the custom lightly doped process used to fabri-
cate Test Chip I.
back plane. For this two port network, the self and mutual im-
pedances can be determined by the resistances as follows:
(8)
(9)
(10)
III. SCM T
EST
CHIPS AND EXPERIMENTAL VERIFICATIONS
To verify the SCM models and extract the needed experi-
mental coefficients, two different lightly doped processes have
been used to fabricate test chips.
A. Test Chip I: Custom Lightly Doped Process
Test Chip I uses a custom lightly doped process. The primary
goal of Test Chip I is to extract the SCM modeling coefficients
and to validate the SCM suitability for a wide range of substrate
port geometries.
Fig. 7 illustrates the cross-sectional schematic view of the
substrate structure used for Test Chip I. A custom lightly doped
process was developed using the Stanford Nano-Fabrication
(SNF) facility. The doping profiles of the substrate, simulated
using Tsuprem [20], are shown in Fig. 8. Fig. 8(a) shows that
the bulk silicon is uniformly doped at
cm and
the p+ diffusion has a peak concentration above
cm .
Fig. 8. Simulated doping profiles of the custom lightly doped process for fab-
rication of Test Chip I. (a) p+ diffusion and p
bulk doping profile. (b) n+ dif-
fusion, N well, and p
bulk doping profile.
Fig. 9. Layout of Test Chip I, showing 1200 SCM test patterns in seven arrays.
Fig. 8(b) shows that the N well depth is about 1 m with a peak
concentration of
cm .
Fig. 9 shows the layout view of Test Chip I. The chip consists
of 1200 test patterns organized in seven arrays, featuring p+ con-
tacts, N well and well ties, and p+ guard rings with combinations
1822 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
Fig. 10. Square contacts with side width
18, 24, 30, 36, and 42
m.
Fig. 11. Arbitrarily sized contacts of 18, 24, 42
m for
6 m,
6 m, and 6 m.
in various sizes, perimeters, and separations, and different posi-
tions of aggressor-victim pairs in a guard ring configuration. It
includes numerous DC probe pads of 80
mby80 m to sup-
port on-chip DC probing.
1) Square and Rectangular Contacts: Figs. 10 and 11 show
the comparison between the measurement data and the SCM
modeling results for sampled structures in Arrays 1–3 of Test
Chip I. Fig. 10 shows the substrate resistance between two iden-
tical square contacts as a function of separation for various con-
tact width of
18, 24, 30, 36, and 42 m. Fig. 11 shows the
substrate resistance between a square contact of 6
m 6 m
and a rectangle contact of 6
m , where 18, 24, and
42
m. It can be seen that in both cases all the coupling re-
sistance trends exhibit a similar behavior: increasing more than
linearly for relatively smaller separations and continuing to in-
crease in a steady linear fashion but with very low slopes for
relatively larger separations. Again, this observation confirms
the near-field and far-field effects. The turning point between
far-field and near-field regions is about 20
30 m, for the cases
Fig. 12. Contacts misaligned with offset.
shown in Fig. 10. As a rule of thumb, the turning point is about
at a spacing equivalent to the size of contact itself. The typical
error falls within 5% with a few exceptions of about 10%. It can
be seen that the SCM model consistently reproduces the data in
both the near-field and far-field regions.
2) Misaligned Contacts: To study the practical situation
where two contact are arbitrarily positioned, the test structures
of contacts misaligned are included in Array 4. The configura-
tion of two contacts misaligned with each other is depicted in
the inset in Fig. 12. The right contact is fixed in position and
sized at 6
mby90 m as a noise aggressor. The left contact
is misaligned to the right one as a noise victim with an offset
varying from 0 to 84
m and sized at 6 mby . The mea-
surement data and modeling results are also shown in the same
figure. The upper and lower set of curves and data correspond to
24 m and 60 m, respectively. The plots clearly
show that the substrate coupling resistance between these two
contacts decreases as the separation
decreases or as the con-
tact sensing area increases. They also show that the strongest
coupling occurs when the left contact is center-aligned with
the right contact. Meanwhile, the coupling resistance increases
by 10% when the left contact moves towards either end of the
right contact for this particular configuration.
Fig. 13 illustrates the configuration of two contacts mis-
aligned with even more offset, namely, super offset,asdefined
in the figure inset. Two different layouts with geometries
labeled are shown in the figure. In this case, the ambiguity of
using the regular edge-to-edge distance can be clearly seen.
Using the concept of GMD, the measure of separation has
been clarified and the model representation is unified. More
importantly it captures the overall geometrical effect of varying
the super offset while fixing the separation
. The measurement
data and the predicted results are drawn in the same figure,
accompanied by the corresponding layout aside. Again, the
model agrees with measurement data well.
3) Guard Ring Structures: Proper deployment and clean
voltage biasing of guard rings can directly help enhance the
sensitive circuits’ immunity to the substrate noise. Hence,
guard ring structures are included in Array 5. Fig. 14 shows a
LAN et al.: SYNTHESIZED COMPACT MODELS AND EXPERIMENTAL VERIFICATIONS FOR SUBSTRATE NOISE COUPLING IN MIXED-SIGNAL ICs 1823
Fig. 13. Contacts misaligned with super offset.
Fig. 14. Noise isolation sensitivity of guard ring width.
typical guard ring protection configuration. The substrate noise
isolation between the aggressor and victim in dB is defined as
(dB) (11)
The noise isolation sensitivity of the guard ring width is
shown in Fig. 14 with both measurement data and modeling
results. As can be seen from the plot, the noise isolation in
dB is roughly proportional to the guard ring width
,in
other words, guard ring size. In this particular case, every
2
m increase in guard ring width gains about 2 dB more noise
isolation. Note that the SCM model gives a good prediction
comparing to the measurement results.
The layout shown in Fig. 15 studies how the positioning of a
noise victim inside a guard ring can affect the noise isolation.
The noise victim is placed in position 1 to 7, as labeled in the
figure. The measurement data is shown in the same figure. It can
be seen that the noise isolation degrades as the victim moves
Fig. 15. Noise isolation sensitivity of noise victim’s location inside guard ring.
from position 1 towards position 4. This is as expected because
during this process a major factor is that the distance between
the victim and aggressor decreases. However, it is more inter-
esting to see that the noise isolation actually becomes enhanced
as the victim continues to move from position 4 to position 7,
by an improvement of 2 dB in this particular case. During this
process a competing factor to the decreasing spacing between
victim and aggressor is the closer and closer distance from the
victim to the guard ring wall. This observation provides a prac-
tical design trade-off when the placement of sensitive circuitry
inside a guard ring is explored. Note that the SCM model gives
a good prediction of the isolation behavior.
B. Test Chip II: 0.18-
m BiCMOS Lightly Doped Process
Based on the experimental verification and observation
from the measured data from the rather large Test Chip I,
another test chip, Test Chip II, was fabricated using a 0.18-
m
lightly doped BiCMOS foundry process. The starting sub-
strate resistivity is 11–16
cm. The sheet resistances of thin
film P-well and N-well regions are 315
110 square and
360
110 square, respectively. A much reduced set of
SCM test patterns were laid out on the second test chip. The
main goal of Test Chip II is to extract and calibrate the SCM
modeling coefficients using a limited number of test structures,
which can be used as a standard bench template for SCM
extraction for other processes.
Fig. 16 shows the die photo of the chip, which consists of a
reduced set of SCM test structures and other mixed-signal cir-
cuit blocks. The dimension of the entire chip is 2 mm by 2 mm.
The SCM test structures include substrate contacts in different
shapes with different sizes, perimeters and separations. On top
of all these substrate coupling ports there are DC probe pads of
70
mby70 m, as can be directly seen in the die photograph.
1) Square Contacts: The minimum unit p+ contact size avail-
able in the process is 0.4
m by 0.4 m. Fig. 17 shows the mod-
eling results and measured data of substrate resistance for square
p+ contact of 1 unit by 1 unit. The separation between the two
0.4
m by 0.4 m contacts varies from 0.5 m to 16.5 m. The
1824 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
Fig. 16. Microphotograph of Test Chip II in a 0.18- m BiCMOS lightly doped
process containing the reduced set of SCM test structures.
Fig. 17. Square contacts on Test Chip II:
m,
m.
measured data show that for this configuration the substrate cou-
pling resistance is as low as around 1.3 k
when the separation
is 0.5
m. As the separation increases, the substrate resistance
first increases steeply and then starts to slow down when the
separation is large enough. The SCM model predicts this trend
well. Another square contact pair configuration with a bit larger
size of 4 units by 4 units, with separation varying from 0.5
m
to 36
m, is shown in the inset of Fig. 18. The side length of
each contact is 1.6
m and thus the contact area is sixteen times
larger than that of the contact in Fig. 17. The comparison be-
tween the measured data and SCM results are shown in Fig. 18.
As can be seen in the figure, the substrate resistance is as low as
about 300
when the separation is 0.5 m and it reaches at a
value around 1.5–1.6 k
when the separation is about 40 m.
2) Rectangular Contacts: The results of two sets of long
rectangular contact configuration are summarized in Figs. 19
and 20. The rectangular p+ contact pair with sizes of 3 units by
10 units and the separation varying from 0.5
mto38 mis
Fig. 18. Square contacts on Test Chip II: m,
m.
Fig. 19. Rectangular contacts on Test Chip II: m,
m.
Fig. 20. Rectangular contacts on Test Chip II: m, m.
depicted in the inset of Fig. 19. The rectangular p+ contact pair
with sizes of 4 units by 20 units and the separation varying from
LAN et al.: SYNTHESIZED COMPACT MODELS AND EXPERIMENTAL VERIFICATIONS FOR SUBSTRATE NOISE COUPLING IN MIXED-SIGNAL ICs 1825
Fig. 21. Comparison of data and SCM model for sample test structures in Test
Chip II. Each contact is sized at
m m.
1.5 m to 55.5 m is depicted in the inset of Fig. 20. In all cases,
the SCM model shows good agreement with the measurements,
giving a mean error of 7% and maximum error of 11%. It is
worth mentioning that the relative error is typically small when
the separation is small and thus the substrate resistance is small.
The larger error typically occurs when the resistance is large. In
other words, the SCM gives better prediction when the substrate
coupling is of greater concern.
3) Arbitrarily Sized Contacts: In order to verify the validity
of the SCM for any arbitrarily sized substrate port configura-
tion, Test Chip II also includes some test structures of this kind.
The inset of Fig. 21 shows the configuration with the contact
dimensions in different sizes and they are also relatively larger
contact area structures compared to those discussed above. For
these structures, the substrate resistance value is on the order of
. The average error is 10% with maximum error 15%.
IV. A
PPLICATION EXAMPLES
A. Guard Ring Modeling
Depicted in Fig. 22 is a typical p+ type guard ring structure
used to reduce the substrate noise impact of an aggressor on a
victim block. The aggressor is 50
mby50 m. The victim is
located at 30
m away and has a size of 50 mby50 m. The
guard ring surrounding the victim is 5
m wide, with the edge to
edge distance of 5
m to the victim. To estimate the effective-
ness of the guard ring deployment, the aggressor, victim, and
guard ring should be considered together. The SCM approach
can be applied to the guard ring configuration to construct an
equivalent circuit model. Since the basic SCM formulation is
for contacts in rectangular shape, it is necessary to decompose
one guard ring into four contacts, one for each of its four sides.
Fig. 23 shows this intermediate step for generating the circuit
model for the guard ring structure. As shown in the figure, the
SCM treats the guard ring structure as a six node network, where
node 1 corresponds to the aggressor, node 2 corresponds to the
victim, and nodes 3 to 6 correspond to the four sides of the guard
ring. Thus, all the substrate coupling resistances indicated in the
Fig. 22. Typical p+ type guard ring structure.
Fig. 23. Intermediate step of circuit modeling using SCM for guard ring struc-
ture.
Fig. 24. Generic lumped equivalent circuit model for guard ring structure.
figure can be calculated using the SCM formula. Subsequently,
considering their parallel connections some resistances can be
combined as follows:
(12)
Fig. 24 shows the final lumped equivalent circuit model of
the guard ring structure. The resistances shown in the figure are
the results from (12). Note that this generic model is a four port
resistance network. It is worth mentioning that the fourth port
denotes the back plane of the substrate, which is normally tied to
GND. However, in some practical situation the back plane has
to be left floating, e.g., when it is used as heat sink for thermal
conduction. It should be emphasized that this generic model is
1826 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
Fig. 25. Davinci simulation results of the guard ring structure. (a) Potential
contours. (b) Current flow vectors in a cross-section view.
well suited for a variety of biasing conditions, guard ring topolo-
gies and back plane connections.
For the guard ring configuration, an effective substrate cou-
pling resistance,
, can be used as a metric of the coupling
strength between the aggressor and victim. It represents the
voltage sensed by the victim due to a unit current noise injected
at the aggressor. The larger the
is, the stronger the sub-
strate coupling occurs between the aggressor and victim. In this
case, the guard ring and back plane are assumed to be ideally
grounded. Then the effective resistance
can be obtained by
computing the equivalent resistance as follows:
(13)
Applying the procedure discussed above to the guard ring
configuration shown in Fig. 22, the resulting effective resistance
is 346.7 . The SCM required only 0.5 seconds of compu-
tation time to get this result as well as the complete equivalent
circuit model.
The most accurate characterization of the guard ring structure
can be obtained using detailed device simulation. Davinci [19] is
used here to study the guard ring configuration shown in Fig. 22.
TABLE I
G
UARD RING EXTRACTION USING SCM VERSUS DAVINCI
Fig. 26. Layout of an ADC prototyping chip in a lightly doped 0.18- m
BiCMOS process.
A total of 47 043 grid points were needed in the Davinci simu-
lations. The computation time was 201 seconds on a SunBlade
100 UltraSPARC IIIi workstation with dual 1.28 GHz CPU and
10 GB RAM. Fig. 25(a) shows the voltage potential contours
when the aggressor is biased at 1 V and both the guard ring and
back plane are ideally biased at 0 V. It can be seen that the poten-
tial falls off rapidly from the aggressor’s location. The grounded
guard ring biases its local region to very low potential. Fig. 25(b)
shows the cross-sectional view of the current flow vectors. It
shows that the currents are injected from the aggressor’s loca-
tion into the substrate. Most of them are removed vertically by
the back plane of the heavily doped substrate. The rest of them
flow to the guard ring and victim region and are absorbed by the
guard ring, which in turn significantly decreases the voltage po-
tential at the victim’s location. The extracted effective coupling
resistance from the Davinci simulation is 306.1
.
Table I summarizes the comparison of the SCM method and
Davinci simulation for this guard ring configuration. Using the
Davinci result as the reference data, the SCM modeling result
has a relative error of 6.8%. In comparing with Davinci extrac-
tion, the SCM is about 400 times faster and still achieves accept-
able accuracy without requiring large number of mesh grids.
B. Full Chip Noise Analysis
This example discusses the application of SCM to support a
simple full chip level substrate noise distribution analysis for
an ADC prototyping test chip, shown in Fig. 26. The chip is
designed using a lightly doped one-poly seven-metal (1P7M)
0.18-
m BiCMOS process. Its dimension is 2 mm by 2 mm. The
circuit blocks that are labeled in the figure include three digital
noise emulators (DNEs), two 4-bit flash ADCs, and two noise
sensors. Initially proposed in [21], the DNEs are used to gen-
erate and dump the digital noise into the substrate. DNE1 and
DNE2 are identical. Each of them consists of an inverter chain
LAN et al.: SYNTHESIZED COMPACT MODELS AND EXPERIMENTAL VERIFICATIONS FOR SUBSTRATE NOISE COUPLING IN MIXED-SIGNAL ICs 1827
Fig. 27. Extracted layout with 319 p+ substrate contacts and two major digital
noise sources recognized and labeled.
TABLE II
SCM E
XTRACTION FOR FULL CHIP
NOISE ANALYSIS
Fig. 28. Full-chip surface substrate noise contours.
with the final stage output driving an explicit capacitor of about
23 pF such that the digital noise can be capacitively injected into
the substrate. DNE3 is simply an inverter chain without any ex-
plicit capacitor. Thus, it is expected to be less capable to inject
noise than DNE1 and DNE2. ADC1 is a 4-bit flash ADC test
structure implemented mostly with CMOS transistors. ADC2 is
another 4-bit flash ADC test structure, now implemented with
the bipolar option available in the process. Sensor1 and sensor2
are two identical differential amplifiers with a p+ contact as the
sensing node.
For the purpose of understanding the substrate noise distri-
bution over the entire chip, the port of primary interest is the
p+ substrate contact (including the p+ guard ring). An SCM-en-
abled CAD tool, Silencer! [22], is used to examine the entire
layout to locate, correctly identify type and to label all sub-
strate ports of interest. It takes about 38 minutes
1
on a Sun-
Blade 100 workstation to examine the entire hierarchical layout
to
locate all the substrate ports. It takes 97 seconds on the same
machine to compute the resistive substrate network using the
SCM model. Fig. 27 shows the extracted view of the layout. A
total of 319 p+ substrate contacts and two major digital noise
sources have been recognized. Aggressor A and B are marked
in the figure, corresponding to DNE1 and DNE2, respectively.
Table II summarizes the node complexity and CPU times re-
quired by the SCM extraction for this full chip example. For
this problem with 319 substrate contacts, the generated SCM
network consists of 1093 resistors.
Subsequently, the full chip surface substrate noise can be sim-
ulated using the extracted substrate network. Fig. 28 show the
resulting noise distribution in terms of equal noise contours for a
perturbation of 300 mV that is injected at aggressor node A and
200 mV injected at aggressor node B, assuming all the substrate
and backside contacts are grounded. It can be seen that the noise
is high in the vicinity of noise source locations. It decays rapidly
in the near-field region. However, it does not decay to zero as it
propagates further into the far-field region. Instead, it approaches
a saturated noise floor of about 30–35 mV for this test chip.
V. C
ONCLUSION
In this paper, a synthesized compact model (SCM) method-
ology for substrate noise coupling analysis is presented. Rig-
orous 3-D device simulations reveal the different coupling be-
haviors in the near-field and far-field regions. Comprehensive
SCM models are developed in terms of
matrix-based for-
mulation for heavily doped substrates and lumped nodal resis-
tance-based formulation for lightly doped substrates. The SCM
models require a set of process-dependent fitting coefficients
and incorporate all geometrical parameters. The method uses
geometric mean distance (GMD) to define the separation be-
tween substrate ports. The SCM approach is validated using
measurements from two test chips and demonstrates an accu-
racy of less than 15% error. The efficiency of generating the
substrate network using the SCM models are demonstrated in
evaluating the guard ring configuration and to a full chip sub-
strate noise distribution analysis.
A
CKNOWLEDGMENT
The authors would like to thank the reviewers for their com-
ments and helpful discussion.
R
EFERENCES
[1] M. Badaroglu et al., “Impact of technology scaling on substrate noise
generation mechanisms,” in Proc. IEEE Custom Integrated Circuits
Conf. (CICC’04), San Jose, CA, Sep. 2004, pp. 501–504.
1
Time for port locating depends on the depth of the layout hierarchy and
layout complexity.
1828 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
[2] R. Gharpurey and R. G. Meyer, “Modeling and analysis of substrate
coupling in integrated circuits,”
IEEE J. Solid-State Circuits, vol. 31,
no. 3, pp. 344–353, Mar. 1996.
[3] N. K. Verghese and D. J. Allstot, “Computer-aided design consider-
ation for mixed-signal coupling in RF integrated circuits,” IEEE J.
Solid-State Circuits, vol. 33, no. 3, pp. 314–323, Mar. 1998.
[4] E. Charbon, R. Gharpurey, R. G. Meyer, and A. Sangiovanni-Vincen-
telli, “Substrate optimization based on semi-analytical techniques,”
IEEE Trans. Comput.-Aided Des., vol. 18, no. 2, pp. 172–190, Feb.
1999.
[5] M. van Heijningen et al., “Analysis and experimental verification of
digital substrate noise generation for epi-type substrates,” IEEE J.
Solid-State Circuits, vol. 35, no. 7, pp. 1002–1008, Jul. 2000.
[6] M. Badaroglu et al., “Methodology and experimental verification
for substrate noise reduction in CMOS mixed-signal ICs with syn-
chronous digital circuits,” IEEE J. Solid-State Circuits, vol. 37, no. 11,
pp. 1383–1395, Nov. 2002.
[7] E. Schrik and N. P. van der Meijs, “Combined BEM/FEM substrate re-
sistance modeling,” in Proc. IEEE Design Automation Conf. (DAC’02),
New Orleans, LA, Jun. 2002, pp. 771–776.
[8] A. Samavedam, A. Sadate, K. Mayaram, and T. Fiez, “A scalable sub-
strate noise coupling model for design of mixed-signal ICs,” IEEE J.
Solid-State Circuits, vol. 35, no. 6, pp. 895–904, Jun. 2000.
[9] D. Ozis, T. Fiez, and K. Mayaram, “A comprehensive geometry-de-
pendent macromodel for substrate noise coupling in heavily doped
CMOS processes,” in Proc. IEEE Custom Integrated Circuits Conf.
(CICC’02), Olando, FL, Sep. 2002, pp. 497–500.
[10] G. V. der Plas, C. Soens, G. Vandersteen, P. Wambacq, and S. Donnay,
“Analysis of substrate noise propagation in a lightly doped substrate,”
in Proc. Eur. Solid-State Device Research Conf. (ESSDERC’04),
Leuven, Belgium, Sep. 2004, pp. 361–364.
[11] M. Pfost, P. Brenner, T. Huttner, and A. Romanyuk, “An experimental
study on substrate coupling in Bipolar/BICMOS technologies,” IEEE
J. Solid-State Circuits, vol. 39, no. 10, pp. 1755–1763, Oct. 2004.
[12] S. Kristiansson et al., “A surface potential model for predicting sub-
strate noise coupling in integrated circuits,” IEEE J. Solid-State Cir-
cuits, vol. 40, no. 9, pp. 1797–1803, Sep. 2005.
[13] H. Lan, Z. Yu, and R. W. Dutton, “A CAD-oriented modeling ap-
proach of frequency-dependent behavior of substrate noise coupling
for mixed-signal IC design,” in Proc. IEEE Int. Symp. Quality Elec-
tronic Design (ISQED’03), San Jose, CA, Mar. 2003, pp. 195–200.
[14] M. van Heijningen et al., “Substrtae noise generation in complex dig-
ital systems: efficient modeling and simulation methodology and ex-
perimental verification,” IEEE J. Solid-State Circuits, vol. 37, no. 8,
pp. 1065–1072, Aug. 2002.
[15] A. Sharma et al., “Accurate prediction of substrate parasitics in heavily
doped CMOS processes using a calibrated boundary element solver,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 7, pp.
843–851, Jul. 2005.
[16] R. Gharpurey, “Modeling and analysis of substate coupling in ICs,”
Ph.D. dissertation, Univ. California, Berkeley, CA, 1995.
[17] F. Grover, Inductance Calculations, Working Formulas and Tables.
New York: Van Nostrand, 1946.
[18] S. Ramo, J. R. Whinnery, and T. V. Duzer, Fields and Waves in Com-
munication Electronics, 3rd ed. New York: Wiley, 1994.
[19] Davinci. Synopsys Inc., Mountain View, CA.
[20] Tsuprem. Synopsys Inc., Mountain View, CA.
[21] Y.-C. Lu, “Digital noise emulator for characterization of phase-locked
loop systems exposed to substrate noise,” Ph.D. dissertation, Stanford
Univ., Stanford, CA, 2004.
[22] H. Lan, M. MacClary, K. Mayaram, T. Fiez, and R. W. Dutton, “Si-
lencer! Pro: a synthesized compact models-based CAD tool for sub-
strate noise analysis,” in Proc. 13th Workshop on Synthesis and System
Integration of Mixed Information Technologies (SASIMI’06), Nagoya,
Japan, Apr. 2006, pp. 207–213.
Hai Lan (S’99) received the B.S. degree in electrical
engineering from Tsinghua University, Beijing,
China, in 1999, and the M.S. degree in electrical and
computer engineering from Oregon State University,
Corvallis, in 2001. He is currently working towards
the Ph.D. degree in electrical engineering at Stanford
University, Stanford, CA. His research interests
include modeling and simulation for mixed-signal
integrated circuits and substrate noise characteriza-
tion, dynamic power integrity, signal integrity, and
high-speed interconnects.
Tze Wee Chen (S’04) received the B.Sc. and M.Sc.
degrees in electrical engineering from Stanford Uni-
versity, Stanford, CA, in 2004 and 2005, respectively.
Since 2005, he has been investigating the impact of
ultra-fast high voltage, high current ESD events on
digital circuits at LSI Logic. He is currently pursuing
the Ph.D. degree at Stanford University, under the
tutelage of Prof. Robert Dutton. His research inter-
ests include modeling gate oxide breakdown due to
ESD events and modeling substrate noise propaga-
tion.
Chi On Chui (S’00–M’04) was born in Hong
Kong. He received the B.Eng. degree in electronic
engineering (highest honors) from the Hong Kong
University of Science and Technology (HKUST) in
1999, and the M.S. and Ph.D. degrees in electrical
engineering from Stanford University, Stanford, CA,
in 2001 and 2004, respectively. His initial research
activities as an undergraduate at HKUST were in
the area of driver circuits design and technology
characterization for display system-on-glass. His
research at Stanford University covered a broad
area in germanium-based devices ranging from process development to
device physics, characterization, and simulation. A major part of his work
was on the seminal integration of high-permittivity gate dielectrics into
germanium channel MOSFETs with significant carrier mobility enhancement
demonstrated. He also maintained a strong interest in germanium-silicon
optoelectronic devices specializing in high-speed and low-noise photodetectors
for monolithic integration.
In September 2004, he joined Intel Corporation as a Researcher-in-Res-
idence at the University of California at Berkeley and Stanford University.
Since September 2005, he has also been appointed a Consulting Assistant
Professor in the Department of Electrical Engineering at Stanford University.
His current research interests include high mobility germanium and compound
semiconductor device physics and technology. He has authored or co-authored
over 60 technical papers (including 17 invited papers), four book chapters, and
three pending patents.
Dr. Chui received his first Best Student Paper Award in the IEEE 60th An-
nual Device Research Conference (DRC) in 2002 and the second Best Paper
Award in the 13th Workshop on Dielectrics in Microelectronics (WoDiM) in
2004. He is also the recipient of the Intel Foundation Ph.D. Fellowship and
the Microsoft Academic Research Grant in 2003. In 1999, he was awarded the
Academic Achievement Award (AAA) by HKUST. He served on the technical
committee for the 2005 IEEE International Conference on Electron Devices and
Solid-State Circuits (EDSSC). He is a member of the IEEE and the Material Re-
search Society.
Parastoo Nikaeen (S’02) was born in Tehran, Iran,
in 1979. She received the B.S. degree in electrical
engineering from Sharif University of Technology,
Tehran, in 2001, and the M.S. degree in electrical
engineering from Stanford University, Stanford, CA,
in 2004. She currently is pursuing the Ph.D. degree
at Stanford University. Her research interests include
modeling and design of analog and mixed-signal
VLSI.
Jae Wook Kim (S’01) received the B.S. degree from
Seoul National University, Seoul, Korea, in 1997, and
the M.S. degree from Stanford University, Stanford,
CA, in 2001 in electrical engineering, where he is
currently working towards the Ph.D. degree. His re-
search interests are mainly in substrate noise analysis
on analog systems such as PLLs and bandgap refer-
ence circuits.
LAN et al.: SYNTHESIZED COMPACT MODELS AND EXPERIMENTAL VERIFICATIONS FOR SUBSTRATE NOISE COUPLING IN MIXED-SIGNAL ICs 1829
Robert W. Dutton (M’70–SM’80–F’84) received
the B.S., M.S., and Ph.D. degrees from the Uni-
versity of California, Berkeley, in 1966, 1967, and
1970, respectively.
He is Professor of Electrical Engineering at
Stanford University and Director of Research in
the Center for Integrated systems. He has held
summer staff positions at Fairchild, Bell Telephone
Laboratories, Hewlett-Packard, IBM Research, and
Matsushita during 1967, 1973, 1975, 1977, and
1988, respectively. His research interests focus on
integrated circuit process, device, and circuit technologies, especially the use
of computer-aided design (CAD) in device scaling and for RF applications.
He has published more than 200 journal articles and graduated more than 48
doctorate students.
Dr. Dutton was Editor of the IEEE J
OURNAL OF COMPUTER-AIDED DESIGN
from 1984 to 1986. He was the winner of the 1987 IEEE J. J. Ebers and 1996
Jack Morton Awards and a 1988 Guggenheim Fellowship to study in Japan, and
was elected to the National Academy of Engineering in 1991, and also been
honored with the C&C Prize (Japan) in 2000. He received a Career Achieve-
ment Award in 2005 from the Semiconductor Industry Association (SIA) for
sustained contributions in support of research that is critical to SIA needs.
