Chi On Chui

University of California, Los Angeles | UCLA · Department of Electrical Engineering and Bioengineering

Field-effect transistor (FET)-based biosensors have demonstrated highly sensitive label-free detection of a plethora of biomolecules as next-generation binding assays. While the dose–response curve of affinity-based binding assays generally has a nonlinear shape, any distortion contributed by the FET transducers has not been well understood. In thi...

We analyzed the low-frequency noise (LFN) of dual-gated field-effect transistor (DG-FET) biosensors with Schottky contacts. We found the flicker noise at the sensing insulator–semiconductor interface to be the major noise source while employing Schottky contacts to have minimal noise contribution with a sufficiently large back-gate bias voltage. Th...

A common setback to electron transport models for quantum cascade laser active regions is the inability to freely simulate widely varying designs. One solution to this problem is to use a density matrix formalism with a generalized treatment of scattering, wherein the well-defined energy eigenbasis is used, and the relative simplicity of the densit...

We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times re...

We derive a density matrix (DM) theory for quantum cascade lasers (QCLs) that describes the influence of scattering on coherences through a generalized scattering superoperator. The theory enables quantitative modeling of QCLs, including localization and tunneling effects, using the well-defined energy eigenstates rather than the ad hoc localized b...

The adoption of spin-transfer torque random access memory (STT-RAM) into nonvolatile memory systems faces three major obstacles: high write energy, low sensing margin, and high read disturbance. Many designs have been suggested to resolve each of these challenges separately and at the cost of significant overhead. We propose a single low-overhead s...

The commercialization of new point of care technologies holds great potential in facilitating and advancing precision medicine in heart, lung, blood, and sleep (HLBS) disorders. The delivery of individually tailored health care to a patient depends on how well that patient's health condition can be interrogated and monitored. Point of care technolo...

While animal experimentations have spearheaded numerous breakthroughs in biomedicine, they also have spawned many logistical concerns in providing toxicity screening for copious new materials. Their prioritization is premised on performing cellular-level screening in vitro. Among the screening assays, secretomic assay with high sensitivity, analyti...

FET-based biosensors (bioFETs) are transistors that can detect and quantify charged molecules, such as DNA, RNA, or proteins, in an aqueous environment. The detection is via the electric charge that such molecules intrinsically carry in aqueous environments, so extra labeling molecules and techniques are not required. As such, these devices hold pr...

Optoelectronic tweezers (OET) has advanced within the past decade to become a promising tool for cell and microparticle manipulation. Its incompatibility with high conductivity media and limited throughput remain two major technical challenges. Here a novel manipulation concept and corresponding platform called Self-Locking Optoelectronic Tweezers...

To exceed the performance limits of dielectric capacitors in microelectronic circuit applications, we design and demonstrate on-chip coplanar electric double-layer capacitors (EDLCs), or supercapacitors, employing carbon-coated gold electrodes with ionogel electrolyte. The formation of carbon-coated microelectrodes is accomplished by solution proce...

We develop an evaluation framework to assess the potential benefits of feature-level heterogeneous integration (HGI) in nanoscale VLSI circuits. We study, for the first time, the impact of HGI on circuit delay, layout area, and power by comparing the integration of 15-nm InGaAs and Ge FinFETs via nanotransfer printing with the baseline Si-only FinF...

Despite many experimental demonstrations of III–V junctionless field-effect transistors (JLFETs), few theoretical studies have investigated their performance. We perform nonequilibrium Green’s function simulations to compare the merits of silicon and In0.53Ga0.47As JLFETs, including impurity, phonon, and surface roughness (SR) scattering effects th...

Random dopant fluctuation (RDF) variability in nanoscale junctionless FETs (JLFETs) utilizing either Si or In0.53Ga0.47As channels has been studied using technology computer-aided design (TCAD) simulations. The 15nm node Si and InGaAs JLFETs are equivalently designed and calibrated using nonequilibrium Green's function simulations for statistical T...

We propose a device, the gate-induced source tunneling FET (GISTFET), that uses two gate work functions to modulate lateral tunneling. The performance of the device is largely independent of the details of the chemical doping profile, potentially freeing device design from issues related to solid solubility, junction abruptness, and dopant variabil...

Intraband source-drain tunneling is predicted to limit leakage current in sub-10 nm field-effect transistors (FETs). We use non-equilibrium Green's function simulations to study this effect in III-V multigate FETs and derive simple, accurate intraband tunneling formulas suitable for use in compact models or semiclassical device simulators. Ban...

This paper reports the fabrication of an electric double-layer supercapacitor that incorporates carbon nanotube electrodes with an ionogel electrolyte based on the sol-gel encapsulation of the ionic liquid, 1-butyl-3-methylimidazolium tetrafluoroborate. The quasi-solid nature of the ionogel electrolyte enables this supercapacitor to become a solid-...

It is commonly believed that small nanowires make more sensitive bioFETs than larger nanowires and planar structures because of the high surface-area-to-volume ratio that is the result of width scaling. We believe this justification is incorrect because it ignores the effect of varying radius of curvature on Debye screening. We suggest an alternati...

Interband tunneling is frequently studied using the semiclassical Kane model, despite uncertainty about its validity. Revisiting the physical basis of this formula, we find that it neglects coupling to other bands and underestimates transverse tunneling. As a result, significant errors can arise at low and high fields for small and large gap materi...

We investigate the applicability of the two-band Hamiltonian and the widely used Kane analytical formula to interband tunneling along unconfined directions in nanostructures. Through comparisons with k·p and tight-binding calculations and quantum transport simulations, we find that the primary correction is the change in effective band gap. For bot...

Capacitors are ubiquitous in signal processing circuits. Dielectric capacitors based on metal-oxide-semiconductor (MOS) and metal-insulator-metal (MIM) designs are currently the industry standard for on-chip charge storage. By comparison, electric double-layer capacitors (EDLC), or supercapacitors, offer capacitances that are orders of magnitude hi...

Significance It is widely believed that surface area-to-volume ratio is directly related to the sensitivity of field-effect transistor-based biosensors; this has led to a massive drive to use nanowires, which are costly and difficult to make, for use in such sensors. Although nanowires do exhibit superior performance in certain situations, we belie...

The continued advancement of digital system performance is arguably the primary reason for the longevity of Moore's Law. However, the RF characteristics of the fundamental digital device, the Si FET, have also become increasingly important considerations for analog and mixed-signal applications. While deeply-scaled Si FETs are now approaching the (...

Evaluation of novel devices in a circuit context is crucial to identifying and maximizing their value. We propose a new framework, PROCEED, and metrics for accurate device-circuit co-evaluation through proper optimization of digital circuit benchmarks. PROCEED assesses technology suitability over a wide operating region (MHz to GHz) by leveraging a...

Stochastic process variability is a major obstacle to scaling field-effect transistor (FET) dimensions toward the nanometer regime. The impacts of line edge roughness (LER), random dopant fluctuation (RDF), oxide thickness fluctuation (OTF), and work function variation (WFV) can significantly affect the performance of individual transistors through...

Investigations on device variability for three different emerging field-effect transistor (FET) technologies are performed to determine the statistical dependence or independence of line edge roughness (LER) and random dopant fluctuation (RDF) variability mechanisms. The device candidates include standard inversion-mode (IM) FinFETs, junctionless (...

In this paper, we review our recent development and validation of the ultrasensitive electronic biomolecular assays enabled by our novel amplifying nanowire field-effect transistor (nwFET) biosensors. Our semiconductor nwFET biosensor platform technology performs extreme proximity signal amplification in the electrical domain that requires neither...

We use pseudo-2-D analytical models to study the electrostatics of multigate tunneling field-effect transistors (TFETs), providing a portable set of equations to simultaneously describe silicon-on-insulator, double gate, and cylindrical nanowire devices. We validate the model via extensive comparisons with numerical simulations and demonstrate its...

In this work, we propose a systematic methodology to calibrate hydrodynamic models against Monte Carlo simulation. Two channel materials (GaAs and Ge) are used to demonstrate the calibration procedure and good fitting of the entire transfer and output characteristics curves is obtained. Further, this approach is scalable to different device dimensi...

In this paper, we develop an evaluation framework to assess variability in nanoscale inversion-mode (IM) and junctionless (JL) fin field-effect transistors (FinFETs) due to line edge roughness (LER) and random dopant fluctuation (RDF) for both six transistor (6T) static random access memory (SRAM) design and large-scale digital circuits. From a dev...

A nanowire-based field-programmable computing platform is presented featuring intrinsic fine-grained device-level reconfiguration without emulation (i.e. no look-up tables involved) using programmable cross-nanowire transistors, and regular physical implementation with relaxed manufacturing requirements at nanoscale. This approach can potentially p...

Parasitics engineering on a GaAs vertical transistor is analyzed. Through separate control of source/drain (S/D) spacer and underlap, the individual impact of the parasitic components is unveiled. Thicker S/D spacer improves $f_{rm T}$, $f_{max}$ by reducing parasitic capacitance. Increased source-side underlap improves output resistance and gain a...

Junctionless field-effect transistors (JL-FETs) contain no doping gradients, so they are thought to be simpler to process and less costly to manufacture than fin field-effect transistors (FinFETs). To check this assertion, process flows for CMOS JL-FETs on 300 mm SOI and bulk silicon substrates with 22 nm gate length are developed, and the manufact...

Emerging nanodevice-based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this article, the impact of parameter variation on nanoscale computing fabrics is extensively studied...

Device-level variability in silicon double-gate lateral tunnel field-effect transistors (TFETs) due to line-edge roughness (LER) and random dopant fluctuation (RDF) is investigated for designs with a 20-nm gate length and body widths of 5 or 10 nm (“20/5” and “20/10,” respectively). Variability in TFET threshold voltage (VT), on-state drive current...

It has been shown that the sensitivity of FET-based biosensors is highest when the biosensor is biased in the subthreshold regime. Given a substrate contact and a solution electrode, there is a wide range of voltages that bias the sensor this way, and not all of them are optimal; we use simulations to clarify the proper bias point. We also show tha...

Tunneling field-effect transistors (TFETs) are being widely investigated as a post-CMOS technology; however, despite significant experimental efforts, no quantitatively accurate device models are available. We derive an expression which provides the complete current characteristics of the double-gate TFET and demonstrate its agreement with simulati...

In order to sustain the historic progress in information processing, transmission, and storage, concurrent integration of heterogeneous functionality and materials with fine granularity is clearly imperative for the best connectivity, system performance, and density metrics. In this paper, we review recent developments in heterogeneous integration...

The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level perspectives using computer-aided design simulations. Resist-defined FinFETs exhibit sizeable device performance variation (up to 10% fluctuation in threshold voltage and 200% in leakage current)...

Parameter variations caused by manufacturing imprecision at the nanoscale are expected to cause large deviations in electrical characteristics of emerging nanodevices and nano-fabrics leading to performance deterioration and yield loss. Parameter variation is typically addressed pre-fabrication, with circuit design targeting worst-case timing scena...

Non-specific binding (NSB), especially due to cross-reactivity between specific capture probes and interferents, is a platform-independent issue that limits the detection selectivity of most affinity-based bioanalytical assays. The ability to differentiate and quantify NSB has thus been sought after particularly in label-free biomolecular detection...

An integrated device-fabric methodology for evaluating and validating nanoscale computing fabrics is presented. The methodology integrates physical layer assumptions for materials and device structures with accurate 3-D simulations of device electrostatics and operations and circuit-level noise and cascading validations. Electrical characteristics...

Junctionless fin field-effect transistor (FinFET) variability due to random dopant fluctuation (RDF) was investigated for sub-32-nm technology generations using technology computer-aided design (TCAD) simulations. Results indicate that variations in threshold voltage, drive current, leakage current, and drain-induced barrier lowering are heavily im...

The work reported here concerns a proposed nanomanufacturing strategy to assemble aligned quasi-one-dimensional nanostructure arrays with intrinsic and concurrent control over the resultant number, pitch, and linewidth. For the first time, a standard lithography and crystallographic etching approach have been combined to synthesize periodic, sublit...

In this paper, we examine the dependence of channel length on the sensitivity of Schottky contacted silicon nanowire field-effect transistor sensors. The fabricated experimental devices are used as photosensors as well as chemical sensors for pH sensing. The difference in light illuminated current response depends on the channel length in the linea...

In this letter, we have demonstrated the integration of phase-change memory (PCM) with thin-film-transistor (TFT) drivers for system-on-panel applications. To overcome the low-current drive and coarse design rule in TFT technology, thermal engineering to concentrate the thermal energy is used to achieve PCM cell programming at a low programming cur...

This paper presents the design of a smart diagnostic capsule system with novel antenna and nano-biosensors. The design of the novel miniaturized antenna addresses some of the challenges in the current capsule diagnostic systems namely potential capsule miniaturization, wireless link robustness for efficient medical data transfer. The implementation...

A simple and reliable one-time-programmable (OTP) memory for low-temperature polysilicon thin-film-transistor technology with metal-induced lateral crystallization (MILC) is developed. The antifuse memory element is based on the breakdown of thin silicon dioxide deposited on smooth surface achieved by MILC. The effects of crystallization process an...

We investigated the variability impact of line edge roughness (LER) on standard inversion-mode (IM) and junc- tionless FinFETs (JL-FinFET) designed for the 2009 ITRS high-performance logic 32-, 21-, and 15-nm nodes using technol- ogy computer-aided design simulations. Fluctuations in thresh- old voltage, drive current, leakage current, subthreshold...

For over one decade, numerous research have been performed on field-effect transistor (FET) sensors with a quasi-onedimensional (1D) nanostructure channel demonstrating highly sensitive surface and bulk sensing. The high surface and bulk sensing sensitivity respectively arises from the inherently large surface area-to-volume ratio and tiny channel...

Junctionless field-effect transistors (FETs) are promising emerging devices with simple doping profiles. In these devices, the channel is uniformly doped without the need for extremely good lateral doping abruptness or high thermal budget at source/channel and drain/channel junctions. This implies that device customization requirements are simplifi...

Several nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. However, their integration and interfacing with external CMOS has received only limited attention. In this paper we explore integration challenges for nanoscale fabrics focusing on regist...

This fabric update summarizes recent advances for the Nanoscale Application Specific Integrated Circuits (NASICs) nanoscale computing fabric. We provide a brief overview of NASICs, and discuss recent work at all fabric levels. We present advances in device design and optimization including omega gated and junctionless nanowire field effect transist...

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration struct...

In this paper, we review a recently developed transformative nanowire FET sensor concept and 3D-compatible fabrication technology. Compared to the generic nanowire FET sensors, an intrinsic boost in detection sensitivity is accomplished through the seamless integration of a sensing nanowire with an amplifying nanowire FET. Exclusively enabled by to...

This chapter provides an overview of the nanoscale application-specific integrated circuit (NASIC) fabric. The NASIC fabric has spawned several research directions by multiple groups. This overview is a snapshot of the thinking, techniques, and some of the results to date. NASIC is targeted as a CMOS-replacement technology. The project encompasses...

In this letter, we present a novel semiconductor nanowire field-effect transistor-based sensing device with an intrinsic amplification mechanism. In this novel device, a nanowire field-effect transistor is integrated with an orthogonal sensing nanowire that amplifies any detected signal. The device operating and intrinsic amplification mechanism ha...

Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on nanoscale computing fabrics is extensively studied t...

We propose a mechanism to explain the excess noise observed in silicon p-n junctions biased at the onset of mixed tunneling and avalanche breakdown. Electrons tunneling into different conduction valleys are treated as separate reaction channels with different impact ionization rates, due to different initial energies, that contribute excess noise....

The low level of output signal in conventional silicon nanowire field-effect transistors (FETs) could limit their potential deployments as integrated chemical and biomedical sensors. We have proposed in this work a novel T-shape channel nanowire FET with a built-in signal amplification mechanism. Compared to the co-fabricated, conventional silicon...

Two novel Permeable Base Transistor (PBT) structures for base leakage suppression with lattice-matched In 0.53Ga 0.47As channel have been proposed. The operations of these novel devices have been analyzed, and their DC and RF performance have been evaluated against the conventional PBT.

By incorporating the realistic junction parameters, we have obtained new insights on practical TFET operation. Interestingly, we have found that a non-abrupt junction does not necessarily degrade the TFET performance if the geometry can be appropriately optimized. We have also studied the tradeoffs in using a Si-Ge-Si channel.

We propose one possible manufacturing pathway for realizing nanodevice based computational fabrics that combines self-assembly based techniques with conventional photolithography. This pathway focuses on realizing the fabric as a whole including assembly of nanostructures, functionalization of devices, contacts and interconnects. Furthermore, this...

We present an integrated approach that combines 3D modeling of nanodevice electrostatics and operations with extensive circuit level validation and evaluation. We simulate crossed nanowire field-effect transistor (xnwFET) structures, extract electrical characteristics, and create behavioral models for circuit level validations. Our experiments show...

Power dissipation has recently overtaken performance as the most important challenge in scaling nanoscale transistors. In this paper, we have proposed and preliminarily analyzed novel device concepts to reduce both the off-state leakage dissipation as well as the dynamic power consumption. The off-state leakage can be selectively suppressed using a...

Both structural and bias asymmetries in double-gate (DG) SOI MOSFET have been critically examined for the sub-60 mV/dec subthreshold swing (SS) possibility. Physical mechanisms are illustrated to explain the inability of all the analyzed structural asymmetries and the feasibility with the bias asymmetries.

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by...

The interface between hafnium oxide grown by atomic layer deposition and (100) GaAs treated with HCl cleaning and (NH4)2S passivation has been characterized. Synchrotron radiation photoemission core level spectra indicated successful removal of the native oxides and formation of passivating sulfides on the GaAs surface. Layer-by-layer removal of th...

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It is believed that below the 65 nm node although conventional bulk CMOS can be scaled, it will be without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65 nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission....

This chapter focuses on advanced germanium metal-oxide-semiconductor device technology including nanoscale gate di-electrics and shallow junctions. The chapter investigates the synthesis and physical properties of germanium oxynitride dielectrics and discusses basic electrical and di-electric-substrate interface characteristics on fabricated german...

This chapter provides an overview on numerous advanced germanium metal-oxide-semiconductor (MOS) devices with a special focus on field-effect transistor (FET) demonstrations reported since 2002. The chapter discusses the urgency and justification to consider a high mobility channel for MOSFET applications and the candidate materials. In the chapter...

Channel materials with high mobility are needed for future nodes to meet the ITRS requirements of MOSFETs. In this work we assess the performance of Si, Ge, and III-V materials like GaAs, InAs and InSb which may perform better than even very highly strained-Si

The electrical properties of Al/LaAlO3/GaAs metal-oxide-semiconductor capacitors were investigated. A thick arsenic (As2) capping layer was used to protect the GaAs surface from oxidation and contamination during the air exposure that occurred between the deposition of the GaAs and LaAlO3 layers in different molecular-beam epitaxy systems. Amorphou...

Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be ach...

The influence of various process conditions on the structural integrity and electrical properties of Al/HfO2/p-In0.13Ga0.87As metal-oxide-semiconductor capacitors was investigated. Room temperature capacitance voltage measurements revealed postdielectric deposition anneal reduced hysteresis by more than 0.5 V and sulfur passivation of InGaAs improv...

We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeOxNy) and tantalum oxynitride (TaOxNy) interface layers. We find that ultrathin interface layers of TaOxNy, a high permittivity diffusion barrier, pr...

A synthesized compact modeling (SCM) approach for substrate coupling analysis is presented. The SCM is formulated using a scalable Z matrix approach for heavily doped substrates with a lightly doped epitaxial layer and using a nodal lumped resistance approach for lightly doped substrates. The SCM models require a set of process-dependent fitting co...

In this paper, atomic layer deposition (ALD) and ultraviolet ozone oxidation (UVO) of zirconium and hafnium oxides are investigated for high-kappa dielectric preparation in Ge MOS devices from the perspectives of thermodynamic stability and electrical characteristics. Prior to performing these deposition processes, various Ge surface preparation sc...

In this paper, nanoscale germanium (Ge) oxynitride dielectrics are investigated for Ge MOS device applications. The synthesizing methodology and physical properties of these oxynitride films have been examined first. Basic electrical characteristics have been acquired on metal-gated MOS capacitors with Ge oxynitride dielectric on substrates with di...

We have studied the effect of varying electrode area asymmetry on the leakage behavior of metal-semiconductor-metal photodetectors (MSM-PDs). We demonstrate, an effective suppression of dark current (Idark) with the application of asymmetric electrode area and appropriate biasing scheme in MSM-PDs. More than 2× reduction in Idark is obtained in pho...

It is believed that below the 65 nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65 nm regime, innovative device structures and new mate rials have to be created in order to continue the historic progress in information processing and transmissi...

3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin wi...

A synthesized compact model of substrate coupling resistance for lightly doped substrate processes is proposed. The model incorporates all geometrical parameters including geometrical mean distance with a few process-dependent fitting coefficients. The model accuracy is shown to be within 15% error using the measurement data from two test chips, on...

A few of the recent unsatisfactory germanium n-channel metal-oxide-semiconductor field-effect transistor MOSFET experimentations are believed to stem from the poor source and drain n+‐p junction formations. In order to explain the primary cause and suggest rectifying solutions, we have examined the activation of common n-type dopants in germanium a...

In this letter, we investigate a method to adjust the gate work function of an MOS structure by stacking two metals with different work functions. This method can provide work function tunability of approximately 1 eV as the bottom metal layer thickness is increased from 0 to about 10 nm. This behavior is demonstrated with different metal combinati...

It is believed that below the 65-nm node the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Example...

We have successfully demonstrated high-performance p-MOSFETs in germanium grown directly on Si using a novel heteroepitaxial growth technique, which uses multisteps of hydrogen annealing and growth to confine misfit dislocations near the Ge-Si interface, thus not threading to the surface as expected in this 4.2% lattice-mismatched system. We used a...

An ultrathin zirconia gate dielectric had been successfully incorporated into germanium metal-oxide-semiconductor (MOS) devices demonstrating very high-permittivity gate stacks with no apparent interfacial layer. In this study, synchrotron-radiation photoemission spectroscopy has been applied on the same gate stack to identify and quantify the pres...

High efficiency and low power photodetectors operating at low absorption regions of silica fibers are attractive for both long distance and chip scale communications. Optical interconnects are promising to alleviate many limitations faced by their electrical counterparts (Miller, 2000). Easy integration of photodetectors with mainstream Si-ICs is a...

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This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We introduce a self-consistent model for calculating device temperature, saturation current and intrinsic gate delay. We show that the raised device source/drain can be designed to simultaneously lower device temperature and parasitic capacitance, such that...

We report on experimental studies of the interfaces formed between high-k metal oxide dielectrics and silicon and germanium (100) substrates. In one case, an oxygen-gettering Ti overlayer was used to decompose the SiO2 interface layer (IL) initially present between HfO2 films and Si, thus reducing the gate stack equivalent oxide thickness (EOT) aft...

It is believed that below the 65-nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission...

The microstructural and electrical properties of Ge-based metal–oxide–semiconductor capacitors containing high- k gate dielectric layers were investigated with and without the presence of a Ge O _x N _y interface layer. The effect of this nitrided layer on thermal stability of the metal oxide/Ge structures was probed by medium e...

We have studied the effect of hydrogen annealing on the surface roughness of germanium (Ge) layers grown by chemical vapor deposition on silicon using atomic force microscopy and cross-sectional high resolution scanning electron microscopy (HR-SEM). Our results indicate a strong reduction of roughness that approaches 90% at 825 °C. The smoother Ge...