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Sequencer Per PinTM Test System Architecture
Burnell West and Tom Napier
Schlumberger Technologies -ATE Division
1601
Technology Dr.
San Jose, CA
951 10-1397
ABSTRACT
This paper describes a novel digital functional test sys-
tem architecture in which the timing and waveform
generation hardware work with a sequence of events
in the same manner as an IC timingllogic simulator.
INTRODUCTION
As the complexity and pin count of VLSl integrated cir-
cuits have exploded, test program generation has be-
come immensely more complicated. VLSl
semiconductor manufacturers are using the data from
the simulation of these complex
IC’s
to
generate timing
information and test vectors for the test program. In
most cases either the input data
to,
or
output data from
the simulator must be modified, before timing and test
vectors can be generated with this simulation data.
This is primarily due to the difference in the technique
in which the simulator and test systems handle wave-
form generation.
TimingAogic simulators work with transitions in the in-
put and output waveforms to the IC which are called
events (i.e. event driven simulation). Test systems gen-
erate waveforms by trying
to
fit a certain format around
these transitions and then programming the time at
which these transitions are
to
occur with edges from a
timing generator. The
IC
simulation is not restricted to
using formats or limiting the number
of
transitions that
occur in a period of time. Often a simulation will con-
tain waveforms that the test system can not produce.
One solution is to perform a special simulation in which
the input data to the simulator has been modified
so
that the simulation will not contain waveforms that can-
not be produced on the test system. Another approach
is to modify the simulation output to make the data fit
the test system. Modifying the input
or
output
of
the
simulation has several negative effects:
Increases test program generation time.
Reduces the accuracy of the test by diverging
Increases debug time
if
modifications to the
from the intent of the simulation.
simulation output create errors.
This paper introduces a new and novel ATE architec-
ture,
sequencer
Per
PlnTM,
in which waveforms are
generated in the same manner as a timing/logic simu-
lator. We will describe how the Sequencer Per Pin
architecture allows waveforms to be generated from
the simulation data using an event sequence concept.
Because this
is
the same concept as used by the sim-
ulator no modifications are necessary to make the sim-
ulation fit the test system architecture. This
architecture reduces the test program generation time,
while insuring that the intent of the simulation is per-
formed during testing. The Sequencer Per Pin archi-
tecture also makes generating hand coded test
programs more straight forward and faster.
BACKGROUND
When digital functional automatic test equipment first
became popular in the latter part of the
603,
its archi-
tecture was very straightforward. Latches written by
controllers formed the stimulus for the device under
test, and comparators on the outputs would verify the
device response. The standard paradigm for digital
functional test was embedded in the ATLAS language
statement “DO-DIGITAL-TEST”, with the logical im-
age of test functionality represented by the diagram of
Figure
1.
Mask
(or
Strobe
Figure
1.
Digital Functional Test Paradigm
The device is driven by FDrv
if
enabled by
I/O.
Other-
wise the device output is compared to FExp as long as
the signal Mask
(or
Strobe) permits. Each succeeding
digital functional test consists of the following se-
quence of events:
Establish the device inputs.
Wait for the device to respond.
1990 International Test Conference
CH2910-6/0000/0355$01
.OO
0
1990 IEEE
Paper 18.2
355
Check the device outputs.
For
each device pin, at any given instant in time at
most one of the following state changes can occur:
Drive to HIGH
Drive
to
LOW
Drive OFF
Begin Test for HIGH
Begin Test for LOW
Begin Test for Z-State
End Test
Complexity arises because different pins require differ-
ent sequences of events, and the timing at which the
state changes are
to
occur will in general vary from pin
to
pin.
Test system architectures in the sixties and seventies
evolved
to
minimize the hardware required to effective-
ly produce large sequences of pin events. This was
necessary, because good test hardware is costly. The
principal architectural innovation of that period was the
separation of functional data from timing, resulting in
the development of very deep pattern memory applied
with shared timing generators (TG’s).[l
J
The functional
data appeared as tables of 1’s and
0’s
(test vectors).
Very effective functional tests could be produced for
complex devices with just a few timing generators con-
nected
to
pattern data by multiplexers and formatters.
But this architectural construction, effective as it was at
that time, introduced difficulties of its own. As devices
became more complex, the process of parsing the test
requirement into the pattern table and the timing be-
came increasingly difficult. Limited numbers of timing
resources inevitably imposed increasingly stringent re-
strictions on their use. The translation from the simula-
tor
output to the test program became increasingly
more obscure and problematical. At the same time, de-
vice speeds dramatically increased, which made test
margins ever more difficult
to
obtain. Pin skew and tim-
ing generator distribution skew began to dominate
tester performance considerations.[2]
During the last decade, TG-per-pin test systems were
introduced
to
help alleviate some of these problems.[3-
61
As more and more resources are applied indepen-
dently
to
each of the device pins, fewer and fewer ma-
chine restrictions are imposed on the functional test
program. But simply applying a TG per pin does not
eliminate the translation problem. The need to modify
the simulation data exists regardless of whether the
test system has shared resource timing or TG-per-pin
timing architecture. The TG-per-pin architecture allows
the flexibility
to
generate independent waveforms on
every device pin, but still restricts the waveforms with
tester oriented formats and limited transitions. Further-
more, many of the available TG-per-pin systems do not
provide calibrated edge placement on all functions.
Thus manual changes to the timing are still required
to
get adequate yields. These restrictions are removed by
providing each pin with a full test event sequence ca-
pability.
SEQUENCER PER
PIN
We define an ‘event’ to be a pair
(s,t),
where
‘s’
is a
state and
7’
is the time associated with a transition
to
‘s’.
An ‘event sequence’ is a time-ordered list of such
pairs. For example, the waveform in Figure
2
here:
I
Figure
2.
is defined by the event sequence
(D1 ,l),(D0,8),( D1,13),( D0,18), interpreted as:
Drive to HIGH at T=l
Drive
to
LOW at T=8
Drive to HIGH at T=13
Drive to LOW at T=18
The seven event types identified earlier are sufficient
to define any digital test completely. Clearly, such a list
can be derived directly from a simulator output. The
goal is
to
apply this simulator data directly
to
the de-
vice. This goal is achieved simply by applying appropri-
ate event sequences, as defined by the simulator
output,
to
each pin independently. For this, we need a
full sequencer
for
each pin.
A
Sequencer Per Pin cir-
cuit contains the local memory, local memory address-
ing, event timing generation, drive and strobe edge
generation, event sequence memory, hardware cali-
bration circuitry, strobe comparison, and fail storage
logic. Each Sequencer Per Pin circuit is independent of
all other pins.
For convenience in pattern storage and human com-
prehension of the test sequence, we do not dispense
with the concept of Fdata entirely. Also to reduce the
amount
of
storage allocated
to
time values, the con-
cept
of
global test period is reintroduced. However, the
global test period is no longer a statement of how fast
the device is running; it becomes nothing more than
a
convenient method of subdividing the test. This results
in the architecture shown
in
Figure
3.
Paper
18.2
356
StimuIuJ~~Response
Period Marker
Master Clock Pin
Figure
3.
Sequencer Per Pin Architecture
The Sequencer Per Pin circuit receives a global period
marker and global event selection. The global event
takes on the appearance of a 'test vector' as defined by
the test systems of earlier architectures. We will use
these terms interchangeably, but the reader is cau-
tioned to keep in mind the distinction. These signals,
together with the master clock, keep all pins synchro-
nized. The stimulus waveforms generated by each Se-
quencer Per Pin are sent to the pin electronics in the
test head. Each Sequencer Per Pin also receives the
DUT output data for comparison after it has been com-
pared to preset thresholds by the pin electronics in the
test head. The period marker consists of a period time
zero event which is synchronized with the master
clock, together with a period vernier value which tells
the Sequencer Per Pin precisely when within the clock
period the event sequence is to begin. The resolution
of the period vernier is the test period resolution (not,
as in many earlier architectures, the master clock
it-
self). Clearly, with this arrangement, there
is
no need
to manipulate the master clock frequency
to
achieve
desired stimulus pattern rates, with the consequent
test program complications.
EVENT GENERATION
Reintroduction of the concept of F-data enlarges the
table of event types. In the current implementation,
pattern memory may contain one or two bits per pin per
global event (test vector). With these additions, events
(now designated
s*,
t*) may be any of the following
types:
DO
-
Drive a
0
D1
-
Drive a 1
DF
DF2
DF-
DF2-
DZ
-
Turn drive off
TO
T1
-
Drive 1st bit LM
-
Drive 2nd bit LM data
-
Drive 1st LM data complement
-
Drive 2nd bit LM data complement
-
Test for a
0
-
Test for a
1
TF
TF2
TE
TF2-
TZ
X
The Sequencer Per Pin circuitry is organized as shown
in the block diagram of Figure 4.
-
Test for 1st bit LM data
-
Test for 2nd bit LM data
-
Test for 1
st
LM data complement
-
Test for 2nd bit LM data complement
-
Test for high impedance
-
Turn window strobe off
The Global Event Selection Signal accesses the event
sequence assigned to each pin in its local event store.
This sequence of events is stored in the form
(9,
t*),
where now
s'
is the expanded table, and
1'
is the time
after the global period commences. This event se-
quence selection is loaded into the circuitry at the clock
cycle containing the period beginning. At the same
time, one or
two
F-data bits are latched from the pin's
local memory, and the period offset (time from clock cy-
cle edge to start of the period)
is
saved up. This action
also initiates a new period count (several period
counters are used, permitting overlap of the calculated
times). The fractional part of the program timet* is add-
ed to the period
off
set, and the result of this calculation
becomes the
cycle-count-plus-vernier
for the specified
edge, but at this point the time value is uncalibrated.
The event type
s'
is converted in the Event Type De-
coder to one of the original seven types.
This
type con-
trols the selection
of
the calibration offset, which is
used to compensate for inevitable path length and cir-
cuit performance differences. To minimize skew from
various state transitions, the calibration store contains
values for different starting states. For example, the
calibration offset associated with
D1
from
Z
is different
from that associated with D1 from
0.
The event time
t*
is calibrated by an event-dependent cal memory. The
calibrated time is designated t".
Additionally, each Sequencer Per Pin can store a se-
quence of 192 events. These may be segmented up to
64
times to give
64
different event sequences per pin.
Event sequences are defined on a per pin basis and
each pin's event sequences are independent of those
on any other pin. This gives the flexibility for 1 pin to
have only a single event sequence with 192 events,
while another pin could have
64
different sequences
with 1,2, or
3
events each. The pins are synchronized
by local event sequence memory (which is similar in
concept
to
a Time Set Memory). A global event se-
quence chooses which event sequence to use of the
64
available for each Sequencer Per Pin. The current
design has memory to store 1024 global event se-
quences, and this memory may easily be expanded to
store 4096 global event sequences. The global event
Paper
18.2
357
Sequence Store Memory
Global Event
(Time Set Memory)
Global
Sequence
--).
4
-t
+
--
Address
Strobe Pin Electronics
Format
+
Logic
Global
Memory
Memory
1
or
2
Bits
per Pin
4
I8
Mbits
Period
Vernier
___fl__
Counters
Period Value,
Global TZ,
Master Clock
(1024x
8)
%=I-
I
t
62
I
Event Time1 Event TvDe
I
I,.
MI
1
+
EventType
Decode
S
Calibrated Time
v
Drive
Edge Generator
Comparator
Edge Generator
Figure
4.
Sequencer Per Pin Block Diagram
II
Signals to
Pin Electronics
p-k
sequence is selected from local memory on a vector by
LOCAL
MEMORY (F-DATA) MEMORY
vector basis.
To
give even greater flexibility in waveform generation,
as for instance when testing devices with long analog
delays, events may be programmed to occur anywhere
within
3
cycles. The resolution of placing the event is
12.5~s. Waveform frequencies can be generated in ex-
cess
of
100
MHz.
As
noted above, each event type generated by the Se-
quencer Per Pin has a unique calibration value which
is used
to
calibrate the event. Each pin has a memory
to
store these values for each event type,
so
the event
is calibrated, “on the fly”, as
it
is
used. This allows the
system to be calibrated with no more than 175ps of
skew between pins.
The local memory has a depth of
4
megabits per pin
and this may be optionally expanded to
32
megabits.
The local memory can be used in a 1 bit
or
2
bit per pin
per vector mode. The
2
bit per pin mode can be used
for presenting
2
bits
of
functional data to a pin in a cycle
such
as required by an
IO
pin where the data driven
to
the DUT is different from the DUT output data. The
second bit may also be used as a mask bit for devices
that require a large combination
of
“care” and “don’t
care” pins in different cycles, such as are frequently
found on
ASIC
simulations vectors.
Each pin in the Sequencer Per Pin design has a
counter
to
control the local memory addressing. This is
very useful in performing scan mode testing since the
local memory for the scan pin may be stepped without
affecting the other pins. The Sequencer Per Pin is also
designed to support alternate sources of data from
Paper
18.2
358
such options as an algorithmic pattern generator or a
super large scan memory. The local memory may be
augmented with an optional subroutine local memory.
Afail memory register is also a part of each Sequencer
Per Pin and this can be expanded to store up to 16K
bits of fail data per pin.
200
MHZ DATA RATES AND WAVEFORMS
Pulse Mode provides a means for generating data
rates up to 200 MHz and clock rates up
to
312.5 MHz
without using pin mux mode. In Pulse mode each drive
event initiates a Return to Zero,
RTZ,
or
Return
to
One,
RTO, pulse depending on the event type, local memo-
ry data, and the pulse direction programmed on a pin.
The width of the pulse on each pin is programmed be-
fore executing the test. The placement
of
the pulse is
determined by the programming
of
the event time.
Pin Mux Mode is also part of the Sequencer Per Pin ar-
chitecture. This allows the Sequencer Per Pin to dou-
ble its frequency and still use all the flexibility
of
event
types. This mode logically
ORs
the timing events and
functional data between
2
adjacent pins to double the
functional data rate and event rate. Each pair of Se-
quencer Per Pin channels may use pin mux mode in-
dependent of any other pin.
IMPLEMENTATION
The Sequencer Per Pin circuit is implemented in a total
of
eight custom integrated circuits. The heart of the cir-
cuit is an ASIC which performs the event generation
and timing. Six calibratable linear delay elements us-
ing
ECL
technology for speed and stability are used to
achieve the required high resolution and accuracy. A
local memory control IC
is
implemented in CMOS.
A
pin slice PCB contains four Sequencer Per Pin chan-
nels.
[ 7-81
Since the local memory, timing, waveform generation,
and calibration circuits are
all
contained on a single
board the configuration of the system is very modular
and easily configured to the user's needs.
Also,
this
partitioning minimizes the number
of
system intercon-
nections and therefore improves the overall reliability.
IC will never exceed
85'
C.
A
low stable junction tem-
perature will greatly decrease component failure and
improve accuracy by preventing component timing
from drifting due
to
temperature changes.[9]
PROGRAMMING THE SEQUENCER PER PIN
The Sequencer Per Pin architecture makes program-
ming complex waveforms very simple. The user only
needs
to
define the type of event and the time at which
the event is to occur. Waveform formats that were
used on the previous generation
of
ATE are easily gen-
erated using the event sequence concept. For exam-
ple NRZ format is specified by programming one
event.
DF@1 ns
This statement directs the hardware to drive
to
the cur-
rent vector's data at InS. The following is a graphical
display of the NRZ waveform.
I
10
to
I
'
D'F
'
DF
SBC format is specified by programming the following
sequence
of
events. This shows the ease with which
other ATE architecture test programs may be ported
to
the Sequencer Per Pin architecture.
D F-@2n
s
DF@ll ns
DF-@22ns
I
to to
1
The high speed sections of the system are liquid
cooled to insure their reliability and stability.
A
cold
plate is attached to each card and a specially designed
heat sink transfers the heat from each component on a
board
to
the cold plate. The cold plate is cooled by re-
frigerated
FC77
liquid circulating through copper tub-
ing. This ensures that the junction temperature on any
Paper
18.2
359
A
clock pin can be generated with no local memory
data by programming the following sequence of
events.
The Following diagram shows a graphical drawing of
this sequence of events:
Dl@Ons
DO@4ns
D1@8ns
DO@
1 Ons
I
to
Different event sequences may be used to change the
number of clocks that occur in a cycle and the place-
ment of the clock transitions. More complex control pin
sequences can also be programmed without the use of
functional data tables at all.
As
a consequence, actual
data pattern storage can be well below one bit per pin
per vector, reducing the demand on pattern storage
space and load times.
Below is an example of waveform generation for an
IO
cycle with the DUT pin being driven with a surround by
complement (SBC) waveform, then the driver being
turned
off
and the output being strobed first for tri-state,
then a
1,
and then local memory data which is different
from the drive data.
D F-@ 2 ns
DF@7ns
OF-@
1
6ns
DZ@20ns
TZ@24ns
X@26ns
T1@32ns
X@34ns
TF2@40ns
X@42ns
Paper
18.2
360
-
Drive functional data complement
-
Drive functional data
-
Drive functional data complement
-
Turn driver off
-
Test for Tri-state
-
Turn window strobe off
-
Test for a 1
-
Turn window strobe off
-
Test for 2nd functional data
-
Turn window strobe off
I
to
TZ
T1
TF2
t
t
tto
I
xx
x
Complex waveforms such as this are not possible on
test systems with shared resource
or
TG-per-pin archi-
tectures. This example used 10 events and the Se-
quencer Per Pin could generate up to 192 events in
one cycle. The ability to have two bits of functional data
in each cycle allows the Sequencer Per Pin architec-
ture to drive one set of data
or
test for a different set in
the same cycle. This is done without using mux mode
which would reduce the available pin count of the test
system. Being able
to
place an event with 12.5~s res-
olution and anywhere across
3
cycles, gives the archi-
tecture even more waveform generation and strobe
placement flexibility. This type of flexibility makes gen-
erating timing statements and test vectors from simu-
lation data fast, easy, and accurate. Eliminating the
need to make the simulation fit the test system will im-
prove the time to generate new test programs, gener-
ate better tests that follow the intent of the simulation,
and decrease the amount of time
to
debug
a
new test
program.
Because the Sequencer Per Pin is truly a complete
functional slice of the tester, including pattern memory
management, another benefit of the Sequencer Per
Pin architecture is
its
ability
to
let the operating system
dynamically allocate test system channels at the time
the test program is installed. To provide the optimum
electrical interface between the test system and DUT
several different pin configurations may exist for a test
program (i.e. wafer
sori
and package part pin configu-
rations). The Sequencer Per Pin architecture allows
each tester channel to be assigned to a device pin at
install time. The tester operating system will prompt the
user for which pin configuration is to be used at install
time. This saves disk space by not having
to
store test
programs and local memory patterns for each DUT
to
test system pin configuration. The logistics of manag-
ing a program library are also eased because only a
single test program and test vector pattern file are re-
quired
for
each device.
Reference:
Software
tools
have been designed
to
work with the
Sequencer Per Pin architecture. These
tools
make
viewing and modifying the test program waveforms
very simple by displaying the waveform graphically
and allowing the user
to
modify the test program via
the graphical display. The changes not only affect the
current tester setup but also may be used to update the
test program automatically.
CONCLUSION
A
revolutionary tester architecture, the Sequencer Per
Pin architecture, has been described. This architecture
implements tests as sequences
of
events for each pin,
synchronized by global period markers. This allows for
performing complex tests on VLSl integrated circuits
without requiring extensive program development and
debug efforts. The automatic generation of these com-
plex waveforms and strobe placement from timing sim-
ulators was not possible on the prior generations of
ATE. In addition, this architecture is more flexible than
previous designs, permitting more precise implemen-
tations of simulation data with fewer restrictions. The
Sequencer Per Pin architecture will decrease the time
needed
to
generate test programs by reducing the
manual intervention required to generate timing and
test vectors from timing/logic simulation data. The
event sequence concept allows significant reduction in
test pattern storage requirements, and optimizes this
feature even further by permitting run-time assignment
of
pin data, avoiding duplications of
test
patterns and
test programs for different package configurations.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Herlein, R.,‘Optimizing the Timing Architecture
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a
Digital LSI Test System’,
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VLSl
Test System’,
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SPP
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Paper
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.
