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Network-on-chip: Current issues and challenges

Authors:
Manoj Singh Gaur
Manoj Singh Gaur
Vijay Laxmi at Malaviya National Institute of Technology Jaipur
Vijay Laxmi
Mark Zwolinski at University of Southampton
Mark Zwolinski
Manoj Kumar at Tata Motors
Manoj Kumar
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Network-on-chip: Current Issues and Challenges
Manoj Singh Gaur
Professor at Computer
Engineering,
Malaviya National
Institute of Technology
MNIT, Jaipur, India
Email:
gaurms@gmail.com
Manoj Kumar
Malaviya National
Institute of Technology
MNIT, Jaipur, India
Vijay Laxmi
Associate Professor at
Computer Engineering,
Malaviya National
Institute of Technology
MNIT, Jaipur, India
Email:
vlaxmi@mnit.ac.in
Niyati Gupta
Malaviya National
Institute of Technology
MNIT, Jaipur, India
Mark Zwolinski
Professor in
the Electronic Systems
Design Group University
of Southampton,
High field, Southampton
SO17 1BJ
Email:
mz@ecs.soton.ac.uk
Ashish
Malaviya National
Institute of Technology
MNIT, Jaipur, India
ABSTRACT
Due to the shrinking transistor sizes, the density of ICs roughly
doubles every year as predicted by Moore’s law. These advancements in the
VLSI integration densities towards the nano scale era, witnessed a paradigm
shift from computation centric designs to communication centric designs
incorporating very large number of simple cores. Plenty of traditional
interconnect schemes like point to point, buses and crossbars are available
to interconnect small number of cores. While achieving fast and efficient
communication with point to point communication schemes, wire density is
a barrier for adapting them to many core architectures. Moreover, buses are
simpler in design, they suffer from the scalability and arbitration issues
along with bandwidth bottleneck as the number of cores increases. Similarly
area and power requirements of a crossbar limits its applicability. Hence, in
many core architectures like Chip Multiprocessors (CMP) and Multi
processor System-on-Chip (MPSoCs), emerge the need of an efficient
communication infrastructure as traditional solutions fails to handle the
communication challenges.
Network-on-Chip (NoC), a scalable and modular design approach, has
been proposed as a promising alternative to traditional bus based
architectures for inter-core communication. NoC has also been accepted in
industy (Tilera’s TILE-Gx72,TILE64TM [1] processors and Intel’s terascale
processor [2]. NoCs are an attractive alternative for the traditional shared-
buses or dedicated wires due to many reasons. First, NoCs represent a
scalable solution to on-chip communication paradigm, because they provide
scalable bandwidth at low power and area overheads. Second, NoCs are very
efficient in terms of use of wiring and multiplexing many traffic flows on the
same channels providing quality of service and higher bandwidth. Finally,
on-chip networks with regular topologies have short interconnects that can
be optimized and reused using regular iterative blocks, thus making the
verification process easy. For on-chip networks, two-dimensional (2D) mesh
is the most preferred topology choice due to its regularity, scalability, and
perfect physical layout on an actual chip. This tutorial shall focus on NoC
routing algorithms, their implementations and issues. The main parameters
of the network which are affected by the routing algorithm include fault-
tolerance, quality of service, communication performance (throughput and
latency) and power consumption. The following are the main objective of this
tutorial:
• Introduction to NoC [3]: In this part, we briefly discuss about various
design parameters of NoC such as topology, switching, flow control,
routing and comparison with existing mechanisms.
• Routing Taxonomy [4]: In this part, we present classification of various
routing algorithms.
• Deadlock and Livelock freedom in Routing: One of current issue in
NoC routing is the use of acyclic channel dependency graph (ACDG)
for deadlock freedom prohibiting certain routing turns. Thus, ACDG
reduces the degree of adaptiveness. In this section, we discuss various
turn models [5] and how these turn model can be improved to
increase adaptivity while maintaining deadlock freedom.
• Routing Implementations for NoC: Denser integration advancements
make the chip more prone to failures (deep sub-micron effects,
manufacturing effects etc). Furthermore these failures may disrupt
the regularity of 2D meshes, leading to an irregular set of topologies
generated from regular 2D meshes. Under this condition, solutions of
regular 2D meshes may no longer work due to irregular topology. In
this section, we discuss state-of-art routing implementation
techniques [6]–[8] used for irregular 2D mesh under different failures.
• Learning methods to handle congestion in Routing: Reinforcement
Learning (RL) is a machine learning paradigm that has been widely
applied in many areas. The Q-Learning has been used in NOC to learn
the network traffic and make the routing decisions accordingly. At
each node, a table is used to store the values that represent the
congestion level of each link and these values are updated after every
packet transfer. Although, Q-Learning has improved network
performance but there are many challenges which we would discuss
in this section
• Brief hands on tool chain for NoC simulation shall also provide
towards the end.
REFERENCES
[1] S. Bell et al., “Tile64 - processor: A 64-core soc with mesh interconnect,”
in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of
Technical Papers. IEEE International, Feb 2008, pp. 88–598.
[2] S. Vangal et al., “An 80-tile sub-100-w teraflops processor in 65-nm
cmos,” Solid-State Circuits, IEEE Journal of, vol. 43, no. 1, pp.
29–41, Jan 2008.
[3] M. Palesi and M. Daneshtalab, Routing Algorithms in Networks-on-Chip.
Springer Publishing Company, Incorporated, 2013.
[4] J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks - An
Engineering Approach. Morgan Kaufmann, 2003.
[5] M. Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, and M. Zwolinski, “A
novel non-minimal turn model for highly adaptive routing in 2d nocs,” in
Very Large Scale Integration (VLSI-SoC), 2014 22nd International
Conference on, Oct 2014, pp. 1–6.
[6] R. Bishnoi, V. Laxmi, M. Gaur, R. Bin Ramlee, and M. Zwolinski, “Ceri:
Cost-effective routing implementation technique for networkon- chip,” in
VLSI Design (VLSID), 2015 28th International Conference on, Jan 2015,
pp. 59–64.
[7] J. Flich and J. Duato, “Logic-based distributed Routing for nocs,”
Computer Architecture Letters, vol. 7, no. 1, pp. 13–16, 2008.
[8] S. Rodrigo et al., “Cost-efficient On-Chip Routing Implementations for
CMP and MPSoC Systems,” Computer-Aided Design of Integrated
Circuits and Systems, IEEE Transactions on, vol. 30, no. 4, pp. 534–
547, 2011.
... In wormhole-switched NoCs, contention between packets causes head-of-line (HoL) blocking, leading to performance ii VOLUME 4, 2016 deterioration or communication failure; thus, deadlock-free is a vital design objective. A deadlock in unicast is mainly caused by a cyclic dependency between packets and is easily rescued by restricting the turn models at the routing stage [15]. However, in multicast routing, different types of deadlocks owing to the branching of packets must also be entirely handled. ...
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  • 88-598
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