Anuj Vaishnav

Xilinx Inc.

FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allow...

FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Conseq...

FPGAs are currently being deployed at a large scale across data-centres for various applications because of their performance and power benefits. In particular, cloud service operators are now offering FPGAs as a Service. However, to completely integrate FPGAs in a data-centre environment like standard software systems, support for fault tolerance...

Despite deployment of FPGAs at the edge and cloud data centers due to their performance and energy advantage, FPGA runtime systems commonly tend to support only one-application-at-a-time and cannot adapt to dynamic workloads with reasonable response times. Therefore, this paper proposes the concepts and theory of resource elasticity for FPGA system...

With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods which can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems need to be maintainable and adaptable to changing workloads while improving accessibility for the application de...

To improve energy efficiency in data centres, in particular when targeting computing with large data-sets, it is vital to perform processing close to the data instead of moving data to compute due to the energy consumption for network usage. For FPGA-based data centres, this is an opportunity to use partial reconfiguration (PR) for moving compute t...

With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods that can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems need to be maintainable and adaptable to changing workloads while improving accessibility for the application dev...

This thesis shows that it is feasible to build modular FPGA systems which can dynamically change the hardware resources in the spatial and the temporal domains using existing tools and accelerators, to improve maintainability, adaptability, and accessibility for FPGA systems. To achieve this, first, a modular FPGA development flow is proposed to bu...

Memory throughput is one of the major bottlenecks for accelerator performance. Now that Zynq UltraScale+ systems are being deployed at exascale to edge, it is important to understand their characteristics of the memory subsystem and optimizations possible for developers. In this paper, we extensively evaluate the memory performance and behaviour fo...

Memory throughput is one of the major bottlenecks for accelerator performance. Now that Zynq UltraScale+ systems are being deployed at exascale to edge, it is important to understand their characteristics of the memory subsystem and optimizations possible for developers. In this paper, we extensively evaluate the memory performance and behaviour fo...

FOS – The FPGA Operating System manages FPGA resources through a resource-elastic scheduler that optimizes the resource allocation for an acceleration task dynamically with respect to the resources available and the current workload of a system. With this, FOS can serve multiple users/application automatically in a runtime system and provides APIs...

This paper introduces ZUCL 2.0, which extends abstraction services for FPGA applications on ARM-FPGA hybrids. The ZUCL 2.0 management services include 1) FPGA multi-tasking and context-switching based on dynamic reconfiguration and cooperative scheduling, 2) communication abstraction based on the ARM AMBA standard, and 3) memory isolation for priva...

This paper introduces ZUCL 2.0, which extends abstraction services for FPGA applications on ARM-FPGA hybrids. The ZUCL 2.0 management services include 1) FPGA multi-tasking and context-switching based on dynamic reconfiguration and cooperative scheduling, 2) communication abstraction based on the ARM AMBA standard, and 3) memory isolation for priva...

The slides were presented by Anuj Vaishnav at HEART 2019 conference on 6th June 2019, for the paper "Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures".

Database sizes are growing faster than the processing power in the post-Moore era due to the advent of big data applications, which make hardware acceleration mandatory. However, currently, database acceleration using FPGAs has mainly been static and with limited accelerator functionality, reducing the potential performance gains from customization...

Heterogeneous computing is a key strategy to meet the requirements of many compute-intensive applications. However, currently, CPU+FPGA platforms are commonly underutilized as scheduling is often constrained to a run-to-completion model or acceleration of a single application at a time. To tackle this, this paper proposes heterogeneous resource-ela...

Heterogeneous computing is a key strategy to meet the requirements of many compute-intensive applications. However, currently, CPU+FPGA platforms are commonly underutilized as scheduling is often constrained to a run-to-completion model or acceleration of a single application at a time. To tackle this, this paper proposes heterogeneous resource-ela...

FPGAs are currently being deployed at a large scale across data-centres for various applications because of their performance and power benefits. In particular, the cloud operators have started providing FPGAs as a Service. However, to completely integrate FPGAs in a data-centre environment like standard software systems, support for fault toleranc...

FPGAs are currently being deployed at a large scale across data-centres for various applications because of their performance and power benefits. In particular, the cloud operators have started providing FPGAs as a Service. However, to completely integrate FPGAs in a data-centre environment like standard software systems, support for fault toleranc...

SRAM-based FPGA devices have been used widely in many industrial domains, but only limitedly in secure and safety-critical applications, which have special requirements for the physical implementation, such as module isolation. This is partly due to limited functionality available with current FPGA vendors' tools and flows. To extend FPGA's appeara...

In this work, we are proposing the ZUCL framework for implementing and running OpenCL applications for the latest Xilinx ZYNQ UltraScale+ platform. ZUCL is a holistic framework addressing the FPGA OS infrastructure, high level synthesis (HLS) module implementation as well as the runtime management. ZUCL enables partial reconfiguration (PR) on this...

FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allow...

FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Conseq...

Many CPU design houses have added dedicated support for cryptography in recent processor generations, including Intel, IBM, and ARM. While adding accelerators and/or dedicated instructions boosts performance on cryptography, we are investigating a different approach that is not adding extra silicon area: We study to replace the hardened NEON SIMD u...