Electronically Tunable DXCCII-Based Grounded Capacitance Multiplier

Abstract

In this paper a new grounded capacitance multiplier based on DXCCII suitable for operation at low and moderate frequencies, is presented. The proposed circuit employs only a single dual-X second-generation current conveyor (DXCCII) active device, used as a voltage amplifier with two NMOS transistors operating in triode region, cooperating with a floating capacitor. The realized equivalent capacitance obtained from Miller multiplication of the reference capacitor and its multiplication factor is electronically tunable. Simulation results using AMS 0.35 μm CMOS process technology parameters are included. Functionality of the proposed circuit is verified through its application in a Gm-C second-order low-pass filter.

Full text

1
P.S.: THIS IS THE PAPER WITH THE AUTHORS’ STYLE.
THE ORIGINAL PAPER WITH THE JOURNAL’S STYLE CAN
BE REACHED FROM THE WEB PAGE OF THE JOURNAL:
(AEU - International Journal of Electronics and Communications)
Electronically Tunable DXCCII-Based
Grounded Capacitance Multiplier
Indrit Myderrizi*1
Ali Zeki2
1. Dogus University, Department of Electronics and Communications Engineering,
Acibadem, Kadikoy 34722, Istanbul, TURKEY, E-Mail: imyderrizi@dogus.edu.tr
2. Girne American University, Department of Electrical and Electronics Engineering,
University Drive, Girne, Mersin 10, TURKEY, E-Mail: alizeki@gau.edu.tr
* Correspondence Author
Abstract— In this paper a new grounded capacitance multiplier based on DXCCII suitable for operation at low
and moderate frequencies, is presented. The proposed circuit employs only a single dual X second-generation current
conveyor (DXCCII) active device used as a voltage amplifier with two NMOS transistors operating in triode region,
cooperating with a floating capacitor. The realized equivalent capacitance obtained from Miller multiplication of the
reference capacitor and its multiplication factor is electronically tunable. Simulation results using AMS 0.35µm
CMOS process technology parameters are included. Functionality of the proposed circuit is verified through its
application in a Gm-C second-order low-pass filter.
Index Terms— capacitance multiplier, DXCCII, grounded, Gm-C filter.

2
1. INTRODUCTION
Most of the circuits in analog integrated systems require the use of the capacitor as a
component. Applications like continuous-time filters, oscillators, resonators, sampled-data
systems etc., may need capacitors with very high values lacking the realization in CMOS
processes due to the large occupied area. Since it is difficult to implement a large capacitor in
an integrated circuit, it is of interest to perform multiplication of small capacitor values using
various active building blocks. Active capacitance multipliers are realized applying voltage-
mode or current-mode capacitor multiplier technique [1]. Recently, several grounded/floating
capacitance multipliers adopting either capacitance multiplication techniques, implemented
using active building blocks such as several classes of second-generation current conveyors
(CCIIs) [2-6], operational transconductance amplifiers (OTAs) [7-8], current conveyor
transconductance amplifiers (CCTAs) [9-10], current mirrors and current amplifiers [11-14],
various active devices; current conveyor and current operational amplifier [15], differential
voltage current conveyor (DVCC) and current controlled current conveyors (CCCIIs) [16],
CMOS inverters and op-amps [17], etc. are reported. Most of the available realizations fail in
one or more of the following subjects: employment of two or more active elements [2-5], [7],
[9], [15-17], excessive use of passive elements [2-3], [15], lack of tunability [2-3], [12], [14-
15], [17], and low frequency restrictions due to parasitic elements [5-6], [9-13]. Thus, it is
essential to realize capacitance multipliers that employ single active element, minimum
number of passive elements, tunable capacitance values and suitable for integration in
applications implemented using CMOS technology.
The paper is organized as follows: in Section 2 the DXCCII active device is introduced. In
Section 3 the proposed DXCCII-based grounded capacitance multiplier is presented. The
nonideality analysis covering mismatching and parasitic elements for the proposed
capacitance multiplier is performed in Section 4 (Details about the effects of imbalance in
differential behavior on the linearity have been supplied in the Appendix section). The
simulation results obtained using SPICE program are emphasized and evaluated in Section 5.
The implementation of the proposed capacitance multiplier in a Gm-C second-order low-pass
filter is given in Section 6. Finally, in Section 7 discussions are made and conclusions are
drawn.
2. THE DXCCII
The dual-X current conveyor (DXCCII) [18], whose electrical symbol is shown in Fig. 1, is

3
a second generation current conveyor with two X terminals (non-inverting Xp and inverting
Xn terminals) with currents reflected to the respective Z terminals (Zp and Zn). As is required
in all CCII topologies, Z and Y are high impedance terminals while X terminal is low
impedance. The defining equations of the ideal DXCCII can be given in the following matrix
form:













































Xn
Xp
Y
Zn
Zp
Xn
Xp
Y
I
I
V
I
I
V
V
I
100
010
001
001
000
(1)
The differential nature of Xp and Xn voltage outputs and availability copies of both IXp and
IXn at Zp and Zn outputs enable efficient and high-linearity realization of transconductors,
filters, amplifiers and analog multipliers with parameters tuned via triode MOSFETs [18-22].
Fig. 2 depicts a CMOS implementation of DXCCII [18].
3. PROPOSED GROUNDED CAPACITANCE MULTIPLIER
The block scheme of the proposed DXCCII-based grounded capacitance multiplier is shown
in Fig. 3. The capacitor C connected between the input and the inverting output of the
DXCCII-based amplifier [20] create an equivalent capacitance Ceq observed between the
input and ground, as a result of Miller multiplication. Defining the inverting gain as -
Kv=Vout2/Vin , routine analysis gives the current IC through capacitor C as
IC=(Vin-Vout2)sC = Vin (1+KV)sC (2)
The DXCCII-based amplifier achieves reverse-phase voltage gains at Vout1 and Vout2
outputs. If loading effect of C can be neglected, the negative voltage gain from Vout2 output
can be written as [20]
 
 
TnC
TnC
M
M
in
out
VVV VV
R
R
V
V
K


22
11
1
2
2


(3)
where RM1 and RM2 are channel resistances of the triode MOSFETs M1 and M2, respectively.
VTn and β=(W/L)μnCox are the threshold voltage and the transconductance parameter for
MOSFETs.
The equivalent capacitance observed between the input node and ground can be given as
   
 
C
VV VV
C
R
R
CK
sV sCKV
sV
I
C
TnC
TnC
M
M
V
in
Vin
in
C
eq 


















22
11
1
211)1(
1


    (4)

4
Obviously, the proposed grounded capacitor can be tuned by the means of VC1 and/or VC2
voltages.
The proposed capacitance multiplier structure supplies a differential voltage across each
triode MOSFET (M1 and M2) which in turn results in even order harmonics cancellation.
Thus, nonlinearities are significantly eliminated [18].
Theoretically, depending on the voltage gain obtained by the amplifier the capacitance
multiplier can achieve very large values. However, in real implementations the oversized
dimensions of the triode MOSFETs limit the value of the obtained grounded capacitance. It
was found that, using the proposed capacitance multiplier to realize a large capacitor can
supply significant area economy compared to an equivalent passive capacitor. For instance,
calculations reveal that, for the used CMOS technology, poly1-poly-2 passive capacitors with
values 11pF and 101pF occupy roughly 7 times and 45 times larger areas than those of the
proposed capacitance-multiplier-based respective implementations (Ceq=11pF and Ceq=101pF
were realized from a reference capacitor of C=1pF, using Kv=10 and Kv=100, respectively.
All tuning voltages were fixed at 1.65V and no further tuning was applied to increase the
gain, thus Ceq). These results obviously reveal the area advantage of the proposed
implementation, besides its tuning capability, which can help increasing the capacitance value
further.
4. NONIDEALITY ANALYSIS
At high frequencies, the parasitic elements of the nonideal DXCCII affect the frequency
response of the proposed grounded capacitance multiplier. The equivalent nonideal model of
DXCCII with the parasitic elements is shown in Fig. 4.
By including the parasitic Y, X and Z terminal resistors and capacitors in the calculations,
we can obtain the frequency-dependent non-ideal behavior of the equivalent capacitor, which
can now be given as a function of s, i.e. as Ceq(s). By assuming CZp=CZn, CXp=CXn, RZp=RZn
and RXp=RXn, which are represented by CZ, CX, RZ and RX, respectively, the admittance of
Ceq(s) can be given as
 
Cs
sC
R
R
sC
R
R
CCsRsCsKsCRssC
X
M
X
Z
Z
M
YYVYYeq 1
//
2
1
////
2
)()(1)( 1
2
11

 
(5)
where, the loading effect of C at the Zn terminal is neglected (valid only for small values of C)
to base the analysis on balanced capacitive loading of Z outputs (Typically, C will not be

5
small, so a capacitive load imbalance will occur at the Z outputs, altering Kv(s), which will be
revealed later. For the sake of simplicity, we will use Eq.(5) at this stage of the analysis).
For CMOS realization, RY is usually very large (because Y input is typically the gate of a
MOSFET), therefore its effect will be negligible even for very low frequencies. Once effect of
RY is neglected, we can decompose Ceq(s) into two components: a fixed part (the offset
component (CY+C) and a frequency-dependent part (Kv(s)C).
By removing the offset value (CY+C) from Ceq, we can obtain its frequency-dependent
component alone. Defining this component as Ceq’(s) = Ceq(s) - (CY+C) and neglecting effect
of RY, we find
C
s
s
s
KC
sC
R
R
sC
R
R
CsKsC
pZ
pZ
zX
zX
pX
pX
V
X
M
X
Z
Z
M
Veq













 0
1
2
1
//
2
1
////
2
)()('
(6)
We see that, Ceq’(s) shows a 2-pole / 1-zero behavior, with
2
//
2
1
2
0M
X
Z
M
VR
R
R
R
K


(7a)
XX
M
pX CR
R






//
2
1
1

(7b)
X
M
zX C
R2
1
1


(7c)
ZZ
M
pZ CR
R






//
2
1
2

(7d)
It is obvious that, low frequency value of Ceq’(s) is Kv0C, which means that low frequency
value of Ceq(s) is CY +(1+Kv0)C. Note that, for low frequencies, Ceq(s) declines from the ideal
value not only due to CY but also due to Kv0 which is different than the ideal value RM2/RM1.
However, these offset and gain errors are not very problematic, since they can be
compensated for (like other errors in a filter application) via automatic tuning. Similarly, gain
errors of DXCCII (the voltage and current gains which are 1 or -1 in Eq.(1)) can be corrected
significantly via automatic tuning. However, if Xp and Xn behavior and/or Zp and Zn behavior
don’t match well, the imbalances may degrade the performance (especially linearity) and
automatic tuning may not overcome completely. The imbalance between Xp and Xn is likely

6
to be worse than the imbalance between Zp and Zn, because Xp and Xn achieve different
voltage gains (+1 and -1, respectively) which require different circuit structures, while Zp and
Zn achieve same current gains (both +1) via simple and almost identical current mirrors. The
details of these tracking mismatch effects on the performance are investigated in the
Appendix section.
Another source of imbalance between Xp and Xn is likely to occur at high frequencies,
because of the different paths the signal experiences from Y to Xp and from Y to Xn (See Fig.
2), which may make the bandwidths of VXp/VY and VXn/VY gain responses different. In such a
case (which is very likely, since obtaining “+1” and “-1” voltage gains requires different
circuit topologies), the linearity will be worse at high frequencies, after a frequency
determined by the lowest-bandwidth response (VXp/VY or VXn/VY). In other words, not only
the bandwidth of the whole system is affected, but also the linearity is influenced due to such
a “bandwidth imbalance”. Such a problem can be solved partly, by setting bandwidths of both
responses equal, via artificial methods (e.g. connecting a small capacitor to move the
bandwidth of the response with higher bandwidth towards the lower one, so as to equalize
both).
Eqs.(5) and (6) are obtained by considering the differential nature of the voltage across Xp
and Xn terminals, which yields the equivalent external resistive loads (due to M1) at these
terminals as RM1/2 both. Similarly, the voltage across the terminals Zp and Zn is assumed
differential, yielding the equivalent external resistive loads (due to M2) at these terminals as
RM2/2 both. Actually, the differential behavior assumption for Zp and Zn is valid for low
frequencies [18], but will be altered for high frequencies, because Zn has an extra connection
to the capacitor C. For small values of C, this effect can still be neglected, yielding Eq.(5).
Otherwise (which is usually the case), an imbalance will be observed at high frequencies,
which will insert an extra pole-zero couple to the Kv(s) transfer function.
It is obvious that the equivalent extra capacitor (in parallel with CZn) at the Zn terminal due
to C can be given as C’=C(1-1/Kv(s)). Note that, for lower frequencies C’≈C (Kv is assumed
large), whereas for high enough frequencies (C starts to exhibit small impedance) Kv≈1,
setting C’ small. By defining a=C’/CZ and conducting relevant analyses, we can reach to the
following expression for Ceq’(s):

7
C
a
as
as
a
s
s
s
KCsKsC
pZ
pZ
pZ
pZ
pZ
pZ
zX
zX
pX
pX
VVeq )2/(2
)2/(2
)1/(
)1/(
)()(' 0





















(8)
where Kv0, ωpX, ωzX and ωpZ are as in Eq.(7a), (7b), (7c) and (7d), respectively.
When we compare Eq.(8) with Eq.(6), we see one new pole at ωpZ/(a+1) and one new zero
at 2ωpZ/(a+2). Note that, a is also frequency-dependent, so the new pole and zero cannot be
treated as completely fixed values. Typically C >>CZ, yielding a large a at low frequencies; so
the new pole will be at relatively lower frequencies compared to ωpZ, nevertheless its effect
will be largely cancelled since it will be followed by the new zero at roughly twice the
frequency. For high frequencies, on the other hand, a=C’/CZ will be small (as discussed
above), so the new pole and zero frequencies will be almost equal, cancelling each other’s
effect. This analysis shows that, the effect of the capacitive load imbalance at the Z terminals
is not very significant, therefore, Eq.(6) can still be used for representing the non-ideal
frequency dependency of the equivalent capacitor.
As revealed above, the frequency response of the utilized DXCCII directly affects the
frequency range. Besides, for large reference capacitor values, the loading effect of C at the
Zn terminal may dictate another bound. Upper limit of the operating frequency of the
proposed capacitance multiplier can be increased by keeping the channel lengths of the used
transistors smaller (so, channel widths will also be scaled down) so as to reduce parasitic
capacitances. However, this will in response degrade the voltage and current tracking
accuracies, so the linearity will be worse. Increasing the bias currents will also work, which
increases the transconductances of the transistors, i.e. they can charge/discharge the parasitic
capacitors faster. However, besides increasing the consumed power, this may also require
wider transistors to handle the large bias currents without causing extra voltage swing
limitations (which will again increase parasitic capacitors). Considering the trade off
relationships and the performance expectations in terms of bandwidth, linearity, power
consumption, area, etc., proper choices can be made for the transistor sizes, bias currents, etc.
during design.
5. PERFORMANCE VERIFICATION
The performance of the circuit in Fig. 3 is verified through PSPICE simulations using
AMS 0.35 µm CMOS process technology model parameters and the CMOS implementation
of DXCCII in Fig. 2 with the aspect ratios given in [18]. Vbias=0.825V is set to supply a
nominal bias current of 10μA. Supply voltages and gate bias voltages of the triode MOSFETs

8
are chosen as VDD=-VSS=1.65V and VC1=VC2=1.65V, respectively. Aspect ratios of the triode
MOSFETs are (W/L)M2=0.5μm/20μm and (W/L)M1=(K0.5μm)/20μm, where K is the factor
determining the voltage gain (Kv) of the amplifier (According to Eq.(3), Kv=K for VC1=VC2.
However, Kv can also be tuned to other values if VC1 or VC2 is varied independently).
DC characteristics of the DXCCII-based amplifier (Fig. 3) for a fixed gain of Kv=K=10 are
shown in Fig. 5. As can be observed, despite the nonlinearities of the triode MOSFETs, the
linearity of the amplifier is quite good for a wide range. This is a result of the differential
voltages across the triode MOSFETs M1 and M2 (See Fig. 3). The linearity can be improved
further (and the gain will be doubled) if the output is taken differentially (Vout,d=Vout1-Vout2)
[18,20], however, it is not easy to benefit from this connection directly, for applying the
capacitor multiplication technique utilized in this work.
Fig. 6 shows the obtained waveforms of the voltage and current through the proposed
grounded capacitance multiplier when gain factor equals 10 and capacitor C is set to 1pF.
From Fig. 6 it can be observed that - as expected - the phase of the current leads that of the
voltage by 90º, similar to that of an ideal capacitor. Frequency response and tuning properties
of the grounded capacitance multiplier are illustrated in Fig. 7. Magnitude and phase
responses of the input impedance of the capacitance multiplier, along with the equivalent
capacitance value are shown. The curves were obtained for β1/β2=10, C=1pF, by keeping
VC2=1.65V constant and sweeping VC1 from 0.95V to 1.65V, by 0.35V steps. The equivalent
low-frequency capacitance values achieved via this tuning process are 2.22pF, 6.50pF and
10.32pF. At low frequencies, the curves are very close to those of ideal passive capacitors.
For higher frequencies, however, the performance is degraded due to the effects explained in
Section 4.
Obtained equivalent capacitance (Ceq) values and errors for different gain factors ranging
from K=1 to 50 and reference capacitors ranging from C=100fF to 100pF (while
VC1=VC2=1.65V), are summarized in Table 1 (Ceq values were extracted from low frequency
response). It can be seen that error increases with the increase of the gain factor K, which can
be explained with the decreased resistance (RM1) of M1 which loads the Xp and Xn terminals.
On the other hand, for a chosen K value, the error is not affected from the increase in
reference capacitor (C) value. However, it should be recalled that as C increases, its
impedance will be smaller, so its loading effect may degrade the behavior (even for low
frequencies).

9
The comparison of performance of the proposed capacitance multiplier with different
active capacitance multipliers is summarized in Table 2. It can be seen that the proposed
capacitance multiplier employs only one single active element with respect to the previously
reported works that use two or more active elements. In contrast with the circuits in [2-3],
[15], that use additional passive elements, the proposed circuit employs only the capacitor
whose value is to be multiplied. It must be noted that the automatic tuning feature makes the
proposed circuit very attractive for applications that require compensation of the parameters’
variations through adjustment of the value of active capacitors.
6. APPLICATION EXAMPLE: TUNABLE GM-C 2ND-ORDER LOW-PASS FILTER
To reveal the functionality of the capacitance multiplier of Fig. 3, a tunable filter
application is used, incorporating the 2nd-order Gm-C low-pass filter shown in Fig. 8. The
grounded capacitors CA and CB are realized with two copies of the proposed capacitance
multiplier. The transfer of the filter can be given as
BA
mm
B
m
BA
mm
in
out
CC GG
C
G
ss
CC GG
V
V
213
2
21


(9)
The parameters ω0 and Q of this filter are,
BA
mm CC GG 21
0

(10a)
A
B
m
mm C
C
G
GG
Q
3
21

(10b)
To simplify the design, we can choose nominal (untuned) values of the capacitors equal
(CA=CB). For this case, Gm1=Gm3=2Gm2 can be chosen (Gm2=Gm , Gm1=Gm3=2Gm) to obtain a
Butterworth filter response (Q=1/√2) nominally. Under these conditions, the resonance
frequency and quality factor can be rewritten as
BA
m
CC
G2
0

(11a)

10
A
B
C
C
Q2
1

(11b)
respectively. Although CA=CB nominally, they are kept separate in the expressions, so as to
explain the tuning possibilities easier.
Independent tuning of ω0 and Q is possible, if CB/CA ratio can be kept constant while
adjusting CACB product, and vice versa.
By considering Eq.(4), we can write CB/CA ratio and CACB product. Since CA=CB nominally,
corresponding capacitance multipliers are identical (reference capacitor C is equal for both
and β1A=β1B, β2A=β2B); only the control voltages (VC1A, VC2A, VC1B, VC2B) can be different
(varied during tuning).
 
 
 
 
TnAC
TnAC
TnBC
TnBC
A
B
VV VV VV VV
C
C







22
11
22
11
1
1




(12a)
 
   
    
  
2
2
1
22
11
2
22
11
22
11 11 



























 C
VVVV VVVV
C
VV VV
VV VV
CC
TnBCTnAC
TnBCTnAC
TnBC
TnBC
TnAC
TnAC
BA






(12b)
The approximation in Eq.(12b) is obtained by considering that, usually a large enough
capacitance multiplication is aimed (i.e. β1>>β2), which makes the 1’s almost negligible.
Eqs.(12a) and (12b) reveal that independent tuning of ω0 and Q is possible by choosing
proper relationships among the control voltages. Independent tuning of ω0 is possible if CB/CA
ratio can be kept constant while adjusting CACB product (So, Q remains fixed while ω0 is
being tuned). Similarly, independent tuning of Q is possible, if CACB product can be kept
constant (So, ω0 remains fixed while Q is being tuned) while adjusting CB/CA ratio (in order to
tune Q).
For simplicity, nominally (for untuned case) the designer can choose all control voltages
equal (VC1A=VC2A=VC1B=VC2B=VC), which yields CB/CA=1 (i.e. Q=1/√2) and CACB≈(β1/β2)2C2
(i.e. ω0≈√2Gm(β2/β1)/C). For independent tuning of ω0, VC1A and VC1B can be adjusted jointly
(VC1A=VC1B), while VC2A and VC2B are kept fixed jointly at their nominal values (VC2A=VC2B). In
this way, CB/CA and thus Q will remain fixed at their nominal values (i.e. CB/CA=1 and at

11
Q=1/√2) during tuning of ω0. Similarly, independent tuning of Q can be performed by
adjusting VC1A and VC2B jointly (VC1A=VC2B), while keeping VC1B and VC2A jointly at their
nominal values (VC1B=VC2A), provided that β1>>β2. In this way, CACB and thus ω0 will remain
fixed at their nominal values during tuning of Q. A detail is that, during tuning of ω0, the
condition “β1>>β2” is not required for keeping Q fixed at its nominal value (Q=1/√2), but will
be required for keeping Q fixed at a pre-tuned value other than its nominal value (Q≠1/√2).
The strategy of tuning may also be changed to solve any other expectations.
The Gm-C second-order low-pass filter of Fig. 8 was designed by using the proposed
grounded capacitance multiplier for realizing CA and CB (K=20 and C=0.5pF were chosen,
yielding Ceq=10.5pF for VC1=VC2). Transconductance values were chosen as Gm1=Gm3=2μS
and Gm2=1μS, resulting in nominal resonance frequency and quality factor values of
f0=21.44kHz and Q=0.707, respectively. For the sake of observing the nonidealities due to the
capacitance multipliers only, the filter was built with ideal Gm equivalents.
The frequency response of the capacitor-multiplier-based Gm-C low-pass filter (for which
CA and CB are capacitance-multiplier-based capacitors) is shown in Fig. 9, along with the
response of the ideal filter (for which CA and CB are ideal capacitors). The deviation from the
ideal response is due to the nonideal behavior of the proposed grounded capacitance
multiplier, which was explained in Section 4.
Tuning properties of the Gm-C 2nd-order low-pass filter are demonstrated in Fig. 10, which
shows the frequency response for different control voltage values. Fig. 10(a) shows the
resonance frequency tuning, which is obtained by changing VC1A=VC1B together, while keeping
VC2A=VC2B=1.65V (constant) to fix Q at 0.707. Quality factor tuning is shown in Fig. 10(b),
which is obtained by changing VC1A=VC2B together, while keeping VC1B=VC2A=1.65V
(constant) to fix f0 at the nominal value 21.44kHz.
7. CONCLUSION
The DXCCII-based grounded capacitance multiplier proposed in this paper employs a
single DXCCII along with two triode MOSFETs which avail tuning. The proposed structure
can be used to realize large capacitance values that are impractical to realize on the chip due
to large area occupied by large capacitors. The electronic tunability feature allows the
proposed capacitance multiplier to be used in different applications operating in low and
moderate frequencies, as integrated continuous-time active filters, oscillators, resonators, etc.,

12
which need electronic tuning. Unlike many tunable circuits for which linearity is sacrificed
for tunability, the linearity of the proposed structure is satisfactory thanks to the differential
voltages across the triode MOSFETs.
APPENDIX
The DXCCII avails an inverted copy of VY voltage at Xn terminal (VXn=-VY) besides the
non-inverted copy at Xp terminal (VXp=VY). Therefore, when a triode MOSFET is connected
between the Xp and Xn terminal for obtaining tunable behaviour (e.g. M1 in Fig. 3), the
voltage across drain and source terminals of the triode MOSFET becomes differential (VXn=-
VXp). As was shown elsewhere [18],[22] the differential voltage across the triode MOSFET
eliminates the even-order nonlinearities (thus, the dominant second order nonlinearities are
eliminated) to supply an almost linear large signal resistance between drain and source
terminals. This can be revealed easily by using the simplified triode region expression:
 
 
 
      
YTnC
Y
YTnYC
XnXp
XnXpTnXnC
DS
DSTnGSXpXnD
VVV
V
VVVV
VV
VVVVV
V
VVVIII
2
2
2
)2(
2
)(
2
2
2
2

























(A.1)
By considering that VDS=VXp-VXn=2VY, we can define a linear resistor (RM=VDS/ID)
between drain and source terminals of the triode MOSFET, of value RM=[β(VC - VTn)]-1,
which is tunable via VC [18], [22].
When a more accurate triode region model is used, we see that odd-order nonlinearities
remain and affect linearity, nevertheless the linearity improvement thanks to the differential
voltage is still very significant [23].
The above behavior can also be regarded as a tunable linear transconductance behavior (Y
is the voltage input and Zp or Zn is the current output of the transconductor), with a
transconductance of [18]
Gm=2β(VC - VTn) (A.2)
This behavior is utilized for obtaining the tunable voltage amplifier.

13
The linearity of the obtained behavior is also affected by the voltage tracking errors at Xp
and Xn outputs which can be modeled as,
VXp = (1+εXp)VY (A.3a)
VXn = -(1+εXn)VY (A.3b)
where εXn and εXp are the relative voltage tracking errors of Xp and Xn outputs. These
nonidealities are likely to alter the balanced differential voltage across the triode MOSFET, so
they affect the linearity. Considering these non-idealities for Eq.(A.1), one can obtain the
following results for the triode MOSFET:
   
 
 
 
 
 
 
 
 
 
 
  



































2
2
)2(
2
11
111
2
)(
2
2
2
2
2
YXnXpXnXp
YXnXpTnC
YXnYXp
YXnYXpTnYXnC
XnXp
XnXpTnXnC
DS
DSTnGSD
V
VVV
VV
VVVVV
VV
VVVVV
V
VVVI





(A.4)
From this relationship, one can obtain the non-ideal version of Eq.(A.2) as
Gm = β[(VC - VTn)(2 + εXp + εXn) - ½(εXp - εXn)(2 + εXp + εXn)VY] (A.5)
One can observe two problems here:
i) The small signal transconductance value (which comes from the first term of Eq.(A.5):
gm=β(VC - VTn)(2 + εXp + εXn) ), is different than the ideal value of (A.2). Nevertheless, this
scaling problem can be overcome by tuning VC. (i.e. when the nonideal gains “1+ εXp” and
“1+ εXn” are far from each other)
ii) The second term (with VY) causes nonlinearity, which cannot be overcome via tuning.
Therefore, it is a more severe consequence of the mismatches in the circuit. This problem is
worse, when the imbalance between Xp and Xn is worse (i.e. when the nonideal voltage
gains “1+εXp” and “1+εXn” are far from each other).
As a numerical example, for |εXp| ≤ 0.05, |εXn| ≤ 0.05 and VY ≤ VC-VTn, we obtain the worst-
case relative scaling error as 5% (obtained for εXp=εXn=0.05) and the worst-case relative
linearity error as 5% (obtained for εXp=-0.05, εXn=0.05).

14
As can be expected, the linearity and scaling errors of the DXCCII-based tunable amplifier
used in this work (See Fig. 3) will be affected by the current tracking errors at Zp and Zn
outputs as well, which can be modeled similarly as, IZp=(1+εZp)IXp and IZn=(1+εZn)IXn,
respectively. Nevertheless, the imbalance at Zp and Zn outputs is less likely to influence
linearity significantly, because the current mirroring circuits from Xp to Zp and from Xn to Zn
are simple and almost identical and also the accuracy can be increased further by applying
cascoding and careful layout techniques. Conversely, the voltage tracking imbalance at Xp
and Xn outputs is likely to be dominant on the overall nonlinearity, due to the different circuit
structures used to achieve “+1” and “-1” voltage gains, from Y to Xp and from Y to Xn,
respectively (See Fig. 2). By considering these facts and for the sake of brevity, the problems
due to current tracking errors at Zp and Zn outputs are not revealed in detail.
REFERENCES
[1] G. A. Rincon-Mora "Active capacitor multiplier in Miller-compensated circuits", IEEE
Journal of Solid-State Circuits, vol. 35, no. 1, 2000, pp. 26-32.
[2] A. A. Khan, S. Bimal, K. K. Dey and S. S. Roy, “Current conveyor based R- and C-
multiplier circuits”, Int J Electron Commun (AEU), vol. 56, no. 5, May 2002, pp.312-316.
[3] A. Lahiri, “DO-CCII based generalized impedance convertor simulates floating
inductance, capacitance multiplier and FDNR”, Australian Journal of Electrical &
Electronics Engineering. vol. 7, no. 1, 2010, pp.15-19.
[4] M. T. Abuelma’atti and N. A. Tasadduq "Electronically tunable capacitance multiplier
and frequency-dependent negative-resistance simulator using the current-controlled
current conveyor", Microelectronics Journal, vol.30, 1999, pp.869-873.
[5] P. Prommee and M. Somdunyakanok, “CMOS-based current-controlled DDCC and its
applications to capacitance multiplier and universal filter”, Int J Electron Commun (AEU),
vol. 65, no. 1, January 2011, pp.1-8.
[6] A. De Marcellis, G. Ferri, N. C. Guerrini, G. Scotti, V. Stornelli and A. Trifiletti, “A novel
low-voltage low-power fully differential voltage and current gained CCII for floating
impedance simulations”, Microelectronics Journal, vol.40, no. 1, 2009, pp.20-25.
[7] W. Jaikla and M. Siripruchyanan, “An electronically controllable capacitance multiplier
with temperature compensation”, Proc. of Int. Symp. on Communications and Information
Technologies (ISCIT 2006), Bangkok, Thailand, 18-20 October 2006, pp.356-359.
[8] A. Jantakun, N. Pisutthipong and M. Siripruchyanun, “Single element based-novel
temperature insensitive/electronically controllable floating capacitance multiplier and its

15
application”, Proc. of Int. Conf. on Electrical Engineering, Electronics, Computer,
Telecommunications and Information Technology (ECTI-CON 2010), Chiang Mai,
Thailand, 19-21 May 2010, pp. 37-41.
[9] T. Kulej, "Regulated capacitance multiplier in CMOS technology", Proc. of 16th Int.
Conf. on Mixed Design of Integrated Circuits and Systems (MIXDES 2009), Lodz,
Poland, 25-27 June 2009, pp.316-319.
[10] P. Silapan, C. Tanaphatsiri and M. Siripruchyanan, “Current controlled CCTA based-
novel grounded capacitance multiplier with temperature compensation”, Proc. of Asia
Pacific Conf. on Circuits and Systems (APCCAS 2008), Macao, China, 30 November - 3
December 2008, pp.1490-1493.
[11] S. Pennisi, "High accuracy CMOS capacitance multiplier", Proc. of 9th Int. Conf. on
Electronics, Circuits and Systems (ICECS 2002), Dubrovnik, Croatia, 15-18 September
2002, vol.1, pp. 389-392.
[12] K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez and S. H. K. Embabi "A 2.4-GHz
monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and
loop capacitance multiplier", IEEE Journal of Solid-State Circuits, vol. 38, no. 6, 2003,
pp. 866-873.
[13] P. Brinzoi, A. Cracan and N. Cojan, "A new approach in designing electrically controlled
capacitance multipliers", Proc. of 10th Int. Symp. on Signals, Circuits and Systems
(ISSCS 2011), Iasi, Romania, 30 June - 1 July 2011, pp.1-4.
[14] Y. Li, A. K. Y. Wong and Y. T. Zhang, “Fully-integrated transimpedance amplifier for
photoplethysmographic signal processing with two-stage Miller capacitance multiplier”,
Electronics Letters, vol. 46, no. 11, 2010, pp. 745-746.
[15] G. Ferri and S. Pennisi, “A 1.5-V current-mode capacitance multiplier”, Proc. of 10th Int.
Conf. on Microelectronics (ICM’98), Monastir, Tunisia, 16-18 December 1998, pp.9-12.
[16] M. Siripruchyanan and W. Jaikla, “Floating capacitance multiplier using DVCC and
CCCIIs”, Proc. of Int. Symp. on Communications and Information Technologies (ISCIT
2007), Sydney, Australia, 17-19 October 2007, pp.218-221.
[17] H. Y. Darweesh, F. A. Farag and Y. A. Khalaf, "New active capacitance multiplier for
low cutoff frequency filter design", Proc. of 19th Int. Conf. on Microelectronics
(ICM’07), Cairo, Egypt, 29-31 December 2007, pp.381-384.
[18] A. Zeki and A. Toker, "The dual-X current conveyor (DXCCII): A new active device for
tunable continuous-time filters", International Journal of Electronics, vol.89, no.12, Dec
2002, pp.913-923.

16
[19] A. Zeki and A. Toker, "DXCCII-based tunable gyrator", International Journal of
Electronics and Communications (AEÜ), vol.34, no.1, 2005, pp.59-62.
[20] A. Zeki and A. Toker, "DXCCII ve doymasız MOSFETler kullanarak sabit kazançlı
kuvvetlendirici tasarımı" ("Fixed-gain amplifier design using DXCCII and triode
MOSFETs"), The 11th National Electrical Engineering Congress, Istanbul,
Turkey, September 2005, pp.417-420.
[21] A. Zeki, A. U. Keskin and A. Toker, "DXCCII-based four-quadrant analog multipliers
using triode MOSFETs", ELECO 2005, The 4th International Conference on Electrical
and Electronics Engineering, Bursa, Turkey, December 2005, pp.41-45.
[22] A.A. El-Adawy, A. M. Soliman and H.O. Elwan, “A novel fully differential current
conveyor and applications for analog VLSI”, IEEE Transactions on Circuits and Systems
II, vol.47, No.4, April 2000, pp.306-313.
[23] Y. Tsividis, M. Banu and J. Khoury, “Continuous-time MOSFET-C filters in VLSI”,
IEEE Journal of Solid State Circuits, vol. SC-21, no.1, February 1986, pp.15-30.

17
Figure and Table Captions
Fig. 1. Symbolic representation of DXCCII.
Fig. 2. CMOS implementation of the DXCCII [18].
Fig. 3. DXCCII-based grounded capacitance multiplier.
Fig. 4. Equivalent nonideal model of DXCCII.
Fig. 5. DC characteristics of the DXCCII-based amplifier.
Fig. 6. Waveforms of voltage and current for the grounded capacitance multiplier of Fig. 3.
Fig. 7. Tuning properties of the grounded capacitance multiplier (top: equivalent capacitance
response, middle: impedance phase response, bottom: impedance magnitude response).
Fig. 8. Gm-C second-order low-pass filter.
Fig. 9. Frequency response of the Gm-C second-order low-pass filter.
Fig. 10. Tuning of second-order low-pass filter’s frequency response through capacitance
multiplier: (a) resonance frequency tuning, (b) quality factor tuning.
Table 1. Equivalent capacitances and errors for different gain factors and reference capacitors
(Ceq values obtained from low frequency capacitance values).
Table 2. Comparison of properties and performance of different capacitance multipliers.

18
Fig. 1. Symbolic representation of DXCCII.
Fig. 2. CMOS implementation of the DXCCII [18].
Fig. 3. DXCCII-based grounded capacitance multiplier.
Fig. 4. Equivalent nonideal model of DXCCII.

19
1.6
1.0
0
-1.0
-1.6
-200 -160 -120 -80 -40 0 40 80 120 160 200
Vin (mV)
Output (V)
Vout1=10Vin
Vout2=-10Vin
Fig. 5. DC characteristics of the DXCCII-based amplifier.
100 120 140 160 180 200 220 240 260 280 300
Time (μs)
20
10
0
-10
-20
30
20
10
0
-10
-20
-30
Voltage
Current
(mV) (nA)
VCeq
ICeq
Fig. 6. Waveforms of voltage and current for the grounded capacitance multiplier of Fig. 3.

20
VC1=1.65V VC2=1.65V
VC1=1.30V VC2=1.65V
VC1=0.95V VC2=1.65V
1.0Hz 10Hz 100Hz 1.0kHz 10kHz 100kHz 1.0MHz 10MHz
Frequency
50
100
150
200
-100
0
100
0
5
10
15
Magnitude (dB) Phase (Degree) Capacitance (pF)
Fig. 7. Tuning properties of the grounded capacitance multiplier (top: equivalent capacitance
response, middle: impedance phase response, bottom: impedance magnitude response).
Fig. 8. Gm-C second-order low-pass filter.
cap-mult. based
passive C
Frequency
1Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz
-30
-20
-10
0
Gain (dB)
Fig. 9. Frequency response of the Gm-C second-order low-pass filter.

21
1.0KHz 3.0KHz 10KHz 30KHz 100KHz
Frequency
-20
-10
-15
-5
0
Gain (dB)
VC1=1.45V
VC2=1.65V
VC1=1.65V
VC2=1.65V
VC1=1.85V
VC2=1.65V
cap-mult. based
passive C
(a)
1.0KHz 3.0KHz 10KHz 30KHz 100KHz
Frequency
0
1
-5
-10
-15
-20
Gain (dB)
cap-mult. based
passive C
VC1A=VC2B=1.45V
VC1B=VC2A=1.65V
VC1A=VC2B=1.85V
VC1B=VC2A=1.65V
VC1A=VC2B=1.65V
VC1B=VC2A=1.65V
(b)
Fig. 10. Tuning of second-order low-pass filter’s frequency response through capacitance
multiplier: (a) resonance frequency tuning, (b) quality factor tuning.

22
Table 1. Equivalent capacitances and errors for different gain factors and reference capacitors
(Ceq values obtained from low frequency capacitance values).
Reference
Capacitor C (pF)
Gain factor
Realized capacitance Ceq (pF)
Obtained / Expected
Error (%)
0.1
1
0.2001 / 0.2
0.05
0.1
5
0.571 / 0.6
-4.833
0.1
10
1.032 / 1.1
-6.182
0.1
20
1.949 / 2.1
-7.190
0.1
50
4.654 / 5.1
-8.745
1
1
2.001 / 2
0.05
1
5
5.707 / 6
-4.883
1
10
10.322 / 11
-6.164
1
20
19.492 / 21
-7.181
1
50
46.542 / 51
-8.741
10
1
20.008 / 20
0.04
10
5
57.068 / 60
-4.887
10
10
103.215 / 110
-6.168
10
20
194.917 / 210
-7.182
10
50
465.417 / 510
-8.742
100
1
200.089 / 200
0.044
100
5
570.682 / 600
-4.886
100
10
1032.152 / 1100
-6.168
100
20
1949.171 / 2100
-7.182
100
50
4654.168 / 5100
-8.742

23
Table 2. Comparison of properties and performance of different capacitance multipliers.
Parameter
Fig. 3
[2]
[4]
[5]
[6]
[9]
[10]
[15]
[16]
Technology
CMOS
0.35μm
AD844
BJT
CMOS
0.25μm
CMOS
0.35μm
BJT
BJT
CMOS
0.5μm
BJT
Type
Grounded
Grounded
Grounded
Floating
Floating
Grounded
Floating
Grounded
Floating
Supply
voltage
±1.65 V
±1.5 V
±2.5 V
±1.25 V
+2 V
±1.5 V
±1.5 V
+1.5 V
±2.5 V
No. active
devices
1 DXCCII
2 nMOS
2 CCII+
2 Buffer
4 CCCII+
3 CCDDCC
1 VCG-CCII
2 CCCCTA
1 DV-CCTA
1 CCII
1 COA
1 DVCC
2 CCCII
No. passive
elements
1C
1C, 2R
1C
1C
1C
1C
1C
1C, 2R
1C
Tunability
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Power
consumption
0.2mW
NA
NA
NA
min 0.7mW
0.822mW
0.48mW
NA
7.32 mW