Abhinav Gupta

Motilal Nehru National Institute of Technology | MNNIT · Department of Electronics & Communication Engineering

Junctionless double gate (JLDG) MOSFET in sub nano meter regime has been the preferred choice for researchers as the leakage current in a JLDG MOSFET is significantly less compared to junction based double gate (DG) MOSFET. Also since the conduction mechanism in JLDG MOSFET is bulk conduction instead of surface channel conduction, the short channel...

Nanotube Junction-less Double-Gate-All-Around (NJL-DGAA) MOSFETs using Si nanomaterials or nano particle emerged as an appealing option for the design of high-speed ULSI processors. Changes in ambient temperature, on the other hand, have an effect on its performance such as hot carrier injection (HCI) degradation, analog/RF performance, and electro...

This paper endeavors to utilize the combined advantages of Hetero-High-K gate stack material on SiGe fin with Junctionless triple gate structure and proposes three devices with different oxide materials and placement. The potential distribution, electrostatic, analog, and RF parameters of the proposed devices are analyzed and compared. Crucial FOMs...

This article presents the analytical modeling of the subthreshold drain current of junctionless channel-modulated double-material double-gate (JL-CM-DMDG) MOSFET. The first time under the full depletion mode, the center channel potential and threshold voltage (VTH) have been derived. The center channel potential has been produced by solving the 2D...

Leakage current in a MOS device has become a bottleneck with the technological growth of semiconductor industry. As the device is scaled down to sub nano meter regime, leakage current components becomes comparable to that of ON-state current. The focus of this paper is to investigate a detailed comparative analysis of various leakage currents prese...

Silicon-based Nanotube Junction-less Double-Gate-All-Around (NJL-DGAA) MOSFETs has become a promising solution to high-speed ULSI chip design. However, the change in surrounding temperature affects its performances, such as hot carrier injection (HCI) degradation, Linearity distortion, and analog performance, which are to be critically analyzed. In...

This present article interprets the analytical models of central channel potential, the threshold voltage, and subthreshold current for Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs. The parabolic approximation equation with appropriate boundary conditions has been adopted to solve the 2D Poisson’s equation for determining the centr...

The channel modulated junctionless gate all around (CM-JL-GAA) MOSFET improves the SCE’s with high graded doping of the channel region. Temperature effects on electrostatic and analog/RF performance of channel modulated junctionless gate all around (CM-JL-GAA) MOSFETs have been explored in this work throughout a temperature range of 200 K to 500 K....

The negative capacitance effect on MOS transistors has lately gained lot of momentum due to the use of ferroelectric material in the gate. They have attracted much attention from researchers due to their improved performance at low power supplies. This work presents the simulation and analysis of NC-CyJLT for analog/RF, linearity distortion, and th...

It is a well-known fact that the gate stacking is used to improve the electrostatic behavior of Si0.5Ge0.5 Junctionless Gate-All-Around (JL-GAA) MOSFETs. In gate stacking, the high-k oxide material is stacked with an interfacial silicon dioxide (SiO2) layer. In the recent past, oxide engineering techniques have been investigated as an alternative a...

In this paper, In0.53Ga0.47As based GAA MOSFETs have been intro-duced and compared with conventional Si-Gate All Around (Si-GAA) MOSFETs for high-performance analog circuits. As InxGa1-xAs is a ternary al-loy (III-V semiconductor alloy), whose properties can be varied by shifting the ratios of InAs and GaAs. Hence there is a necessity to evaluate t...

The In0.53Ga0.47As-Based Double-Gate-All-Around (DGAA) device has been proposed using the ternary alloy (III-V semiconductor alloy). The composite material properties of InxGa1-xAs have been modified by changing the ratio of InAs and GaAs. The modified composite material has enhanced the electron mobility with a much higher value. Thus, the In0.53G...

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic...

Low power, low cost, less chip area, and high speed have become the requirements in the present generation of electronic circuits in nano-sacle technology. Due to the requirement of high speed, small silicon chip area, and low power consumption of VLSI circuits, CMOS technology is scaled down. This paper proposes a novel circuit to improve the circ...

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic...

In this paper, analytical modeling of center channel potential has been performed for graded-channel gate-all-around (GC-GAA) junctionless field-effect transistor (JLFET). The three-dimensional (3D) Poisson’s equation has been solved to discover the center channel potential utilizing the parabolic approximation equation with excellent boundary cond...

This present article interprets the analytical models of central channel potential, the threshold voltage, and subthreshold current for Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs. The parabolic approximation equation with appropriate boundary conditions has been adopted to solve the 2D Poisson’s equation for determining the centr...

Junctionless transistors in the present day scenario are the trend which the engineers are focusing onto. These devices are not only small scale but also devoid of the effect of junctions. This research paper presents a detailed analysis of the effect of various parameters like fin width, fin height, gate work function, and oxide thickness. The ana...

In this paper, The gate-material engineering technique is used on double gate all around (DGAA) MOSFET. The gate material engineering technique has two dissimilar materials with dissimilar work functions. The different materials have combined to make a single gate MOSFET. The silicon-tube double-gate-all-around MOSFET have two gates. There are one...

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/...

This paper discusses and analyzes, doping-less dual-material-double-gate (DL-DMDG) silicon-germanium (Si–Ge) MOSFET using oxide engineering technique. In oxide engineering technique, the dual material gate oxide is used in such a way that the permittivity of oxide under the control gate is less than that of screening gate (1 < 2). Such an arrangeme...

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson's equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction...

This paper presents a novel approach to design robust source coupled logic for implementing ultra low power circuits. In this paper, we proposed two different source coupled logic structures and analyzed the performance of these structures with STSCL. The first design we used DTPMOS as load device and analyses the performance of DTSCL Logic with pr...

This paper presents a novel approach to design robust source coupled logic for implementing ultra low power circuits. In this paper, we proposed a dynamic threshold source coupled logic and analyses the performance of dynamic threshold source coupled logic with previous source coupled logic for ultra low power operation. Dynamic threshold source co...