blueice BVBA, Zaventem, Belgium
Question
Asked 5th Sep, 2016
What is a proper test-bed for full adders in VLSI designs?
With referring to the topic below
- If the test-bed I used is not a proper one to test driving capability of full adders, can the attached test bed provides the sufficient conditions? Or can I use a ripple carry adder test bed instead of that?
- Last question: Can I use same input pattern for all of the A1, A2...An or B1,B2,...Bn inputs in RCA test-bed?
Most recent answer
Dear Madam,
This is a gate-level issue. You can expect issues like this in deep-submicron technology. What you see in the diagram, is that the propagation through the ripple chain of each full adder, slows down the slew rate of the signal. This is typical in deep submicron, where only the inverters and to a limited extend, the NAND2 gates are able to keep the slew rate of the propagating signals. All other gates tend to lose slew rate.
This issue should be prevented in logic synthesis. Logic synthesis should be done such that, the minimum slew rate is respected. (this is a logic synthesis constraint.)
Obviously, here it went wrong !. You should not debug this in simulation, but in logic synthesis, and in running timing check tools. So, the question to you obviously is:
(1.) How did you run logic synthesis ?. (If at all, if you did not, please do.)
(2.) What timing check tool did you use ?.
(3.) What minimum slew rate did you specify ?.
Best Regards,
Henri.
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All Answers (4)
University of Isfahan
HI
I think your out put is not full swing and also the loading capacitances are not chosen properly.
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Islamic Azad University Tabriz Branch
Majid Amini Valashani
Thanks for your comprehensive reply! I admit your descriptions.
But just at this part:
- the reported “Power” is
- "Power consumption of full-adder” + “Power consumption of input and output inverters”
- To overcome this problem, you should use 2 different supply voltages in your HSPICE code. One for full-adder and one for inverters."
Can you expand it? As far as I know it is possible to consider two different delays, but I dont know what do you mean about considering two supply voltages to obtain power consumption (although i think i have seen this case in another article too). I considered a total power for all test bed(3).
Thanks Mohammad Reza Reshadinezhad,
I considered Cload values by imitating other articles, in fact I do not know how to obtain their values in CNTFET-based circuits.
Islamic Azad University Tabriz Branch
Majid Amini Valashani
Thank you very much! You have described clearly.
It is a maybe heavy news for me because I should simulate again all of my circuits, and you know, the CNTFETs have a long -time simulation.However thank you so much for sharing your knowledges with me.
blueice BVBA, Zaventem, Belgium
Dear Madam,
This is a gate-level issue. You can expect issues like this in deep-submicron technology. What you see in the diagram, is that the propagation through the ripple chain of each full adder, slows down the slew rate of the signal. This is typical in deep submicron, where only the inverters and to a limited extend, the NAND2 gates are able to keep the slew rate of the propagating signals. All other gates tend to lose slew rate.
This issue should be prevented in logic synthesis. Logic synthesis should be done such that, the minimum slew rate is respected. (this is a logic synthesis constraint.)
Obviously, here it went wrong !. You should not debug this in simulation, but in logic synthesis, and in running timing check tools. So, the question to you obviously is:
(1.) How did you run logic synthesis ?. (If at all, if you did not, please do.)
(2.) What timing check tool did you use ?.
(3.) What minimum slew rate did you specify ?.
Best Regards,
Henri.
1 Recommendation
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