Question
Asked 12th Jun, 2016

How to simulate Si-Based Double Gate MOSFET in Silvaco ATLAS?

I have been trying to simulate silicon-based DG MOSFET using Silvaco ATLAS. I have been using NEGF model for that. But the results that I have obtained is not correct. 
Is there any example that can help me to solve this problem? 

Most recent answer

Safayet Ahmed
Oregon State University
Girish Wadhwa Thank you for sharing. It is indeed an informative playlist for Silvaco TCAD.
If I have any questions I will contact you.

Popular answers (1)

As far as subthreshod slope is concerned, the choice of transport model should not affect your results. The subthreshod slope and in general other metrics of the electrostatic integrity of the device such as DIBL or threshold voltage roll off depend on many things, including your channel thickness, gate dielectric thickness and the details of your junction design. For a ~10nm gate length you'll need a channel thickness of 3-4nm and gate dielectric thickness of 1nm or less and very sharp junctions, like 1nm/dec.
3 Recommendations

All Answers (7)

Please be specific on why you think the results are not correct. It also helps if you start with the simplest physics models such as drift diffusion transport and then add more complex models.
2 Recommendations
Safayet Ahmed
Oregon State University
I was trying to simulate MOSFET of 10 nm gate length. I have found on some previously published paper that the subthreshold slope of this gate length MOSFETs is around 85 mV/decade.
But I got SS around 290 mV/decade. That's why I am assuming my results are not correct. 
And I will try with drift diffusion model. Thanks for the Suggestion. 
1 Recommendation
As far as subthreshod slope is concerned, the choice of transport model should not affect your results. The subthreshod slope and in general other metrics of the electrostatic integrity of the device such as DIBL or threshold voltage roll off depend on many things, including your channel thickness, gate dielectric thickness and the details of your junction design. For a ~10nm gate length you'll need a channel thickness of 3-4nm and gate dielectric thickness of 1nm or less and very sharp junctions, like 1nm/dec.
3 Recommendations
Safayet Ahmed
Oregon State University
Dear Ali Khakifirooz, 
Thank You for your valuable comment. It will help me a lot in my work. 
Shruti Mehrotra
GlobalFoundries Inc.
Hello, 
I'm simulating a short channel double-gate MOSFET using Silvaco ATLAS employing NEGF transport. But my off current is too high. Can u please tell me what scattering models should be used with it? 
Best wishes,
Shruti.
Safayet Ahmed
Oregon State University
Hello Ms. Shruti,
For Double gate MOSFET I have solved SCHRODINGER equation in Non Equilibrium Green's Function (NEGF) approach in the mode (subband) space. 
I have considered fully depleted ballistic (no scattering) nMOSFETs. That's why no scattering model haven't been specified. 
You can check Quantum x 12 Example for simulating DG MOSFET using NEGF transport.
Safayet Ahmed
Oregon State University
Girish Wadhwa Thank you for sharing. It is indeed an informative playlist for Silvaco TCAD.
If I have any questions I will contact you.

Similar questions and discussions

What causes this warning in Silvaco TCAD?
Question
3 answers
  • Wang RickWang Rick
Thank you for answering my question, dear Sir/Madam:
I tried to simulate an FTJ structure with ATLAS in Silvaco TCAD, and this warning occured:
Warning: Internal error in linear solver.
This situation rarely occurs in normal circumstances.
This error could indicate a ill-defined problem.
Check structure and models for possible conflicts.
Warning: Cannot trap. Cannot reduce bias
step. Choose smaller bias step size, or
check structure and or models.
below is my source code, and I wonder what's wrong with it:
go atlas
mesh outf=meshferro.str
x.m loc=0.0 spacing=0.001
x.m loc=0.1 spac=0.001
#
y.m loc=-0.3 spacing=0.01
y.m loc=0.0 spacing=0.01
y.m loc=-0.1 spacing=0.001
y.m loc=-0.108 spacing=0.001
y.m loc=0.5 spac=0.01
#
region num=1 silicon y.min=0.0
region num=2 material=tin y.max=0.0 y.min=-0.1
region num=3 material=hfo2 y.max=-0.1 y.min=-0.104
region num=4 material=zro2 y.max=-0.104 y.min=-0.108
region num=9 material=al2o3 y.max=-0.108 y.min=-0.110
region num=10 material=al y.max=-0.110 y.min=-0.3
#
electrode top name=gate
electrode bottom name=sub
#
doping region=1 conc=1e15 uniform p.type
save outf=ftj04.str
tonyplot ftj04.str
#
models region=3 ferro
material region=3 ferro.ec=20e3 ferro.pr=0.5e-6 ferro.ps=1.0e-6 ferro.epsf=200
method newton trap
#
solve vgate=-5
probe x=0 y=-0.3 dir=90 polarization
#
log outf=ferro04.log master
#
solve name=gate vfinal=5 vstep=0.05 ac freq=1e-6 direct
material region=3 ferro.ec=-20e3
#
solve name=gate vfinal=-5 vstep=-0.05 ac freq=1e-6 direct
#
tonyplot ferro04.log -set ferroex01_0.set

Related Publications

Preprint
Design and study of Ion-Implanted MOSFET's with channel length (18 nm) using Silvaco's International
Presentation
this describe How SILVACO Works and how to simulate MOSFET or other Devices using ATHENA and ATLAS. It will also describe difference between ATLAS and ATHENA.
Article
In this work, numerical simulation methods have been applied to a 4H–SiC trench-gate MOSFET structure to investigate its susceptibility to single event burnout. With SILVACO ATLAS, the high-k shielded trench-gate MOSFET and high-k trench-gate MOSFET are investigated to prove that P+ shielding region under the trench bottom could provide a leaking p...
Got a technical question?
Get high-quality answers from experts.