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shows the block diagram of an MPEG-4 decoder. The incoming bitstream is demultiplexed into several elementary streams. After syntax decode and bitstream parsing, scenedescription, control information and variable-length coded data of audiovisual objects are extracted. These objects are then decompressed and collected in an object pool memory. The scene is generated in the compositor from this data basis. In this final step objects may be manipulated, e.g. zoomed, moved, rotated or even cuted from the scene. Compositing includes complete 3D rendering of synthetic objects using a VRML-like scene description in binary format (BIFS).
Source publication
This paper proposes a new array architecture for MPEG-4 image
compositing. The emerging MPEG4 standard for multimedia applications
allows script-based compositing of audiovisual scenes from multiple
audio and visual objects. MPEG-4 supports both, natural (video) and
synthetic (3D) visual objects or a combination of both. Objects can be
manipulated,...
Citations
Multimedia processing is becoming increasingly important with wide variety of applications ranging from multimedia cell phones to high definition interactive television. Media processing techniques typically involve the capture, storage, manipulation and transmission of multimedia objects such as text, handwritten data, audio objects, still images, 2D/3D graphics, animation and full-motion video. A number of implementation strategies have been proposed for processing multimedia data. These approaches can be broadly classified into two major categories, namely (i) general purpose processors with programmable media processing capabilities, and (ii) dedicated implementations (ASICs). We have performed a detailed complexity analysis of the recent multimedia standard (MPEG-4) which has shown the potential for reconfigurable computing, that adapts the underlying hardware dynamically in response to changes in the input data or processing environment. We therefore propose a methodology for designing a reconfigurable media processor. This involves hardware–software co-design implemented in the form of a parser, profiler, recurring pattern analyzer, spatial and temporal partitioner. The proposed methodology enables efficient partitioning of resources for complex and time critical multimedia applications.
This paper presents our studies on the effects of using SIMD processor extension developed to enhance the processor performance for streaming applications. Our approach was evaluated using MPEG-4 encoding application as benchmark. Although MPEG-4 consists of many different operations, we concentrated on the sum of absolute differences (SAD), a major part of the motion estimation. The SAD was chosen because it is one of the most frequently used operations in MPEG-4 encoding. It is estimated to consume between 40%-80% of the total video encoding time when implemented on a general purpose processor. We have performed an extensive evaluation of our architecture extension. This evaluation showed that it is possible to achieve high performance with acceptable power consumption. We obtained about two times performance improvement for MPEG-4 encoding with roughly the same power consumption.
In this work, the instruction-level and function-level profile analyses of a MPEG-4 video encoder are performed to design a reconfigurable digital signal processor (DSP) architecture. According to the result from the instruction-level profile analysis, the proposed DSP architecture would be lined up with 5 arithmetic logic units (ALUs), 1 multiplier, and 2 load/store units. Such a line-up in the computation units would allow the proposed DSP architecture to have a better parallel processing capability and a higher hardware usage rate in realizing the MPEG-4 video encoder. The result from the function-level profile analysis reveals that the function of motion estimation requires the most computation power. Hence, the proposed DSP architecture reconfigures 4 ALUs and a multiplier to become a functional unit for high parallel processing of motion estimation. This hardware design of motion estimation is primarily dependent on the adders and multiplier of the proposed DSP architecture, plus a few control circuits to convert the computation units. Such arrangement would have less hardware cost than in conventional video processors with specialized functional units for motion estimation. Lastly benchmark analysis and comparison are done between the proposed DSP architecture and TI TMS320C64x architecture. In processing the MPEG-4 video encoder, the proposed DSP architecture is as much as 80% more efficient in computation than the TI TMS320C64x architecture.
Multimedia processing is becoming increasingly important with a wide variety of applications ranging from multimedia cellphones to high-definition interactive television. Media processing involves the capture, storage, manipulation and transmission of multimedia objects such as text, handwritten data, audio objects, still images, 2D/3D graphics, animation, and full-motion video. A number of implementation strategies have been proposed for processing multimedia data. These approaches can be broadly classified based on the evolution of processing architectures and the functionality of the processors. In order to provide media processing solutions to different consumer markets, designers have combined some of the classical features from both the functional and evolution-based classifications resulting in many hybrid solutions. We propose a categorization of existing microprocessors based on a combination of both architectural and functional flavors with examples of each approach from the latest multimedia processing families. The varying processing requirements in multimedia computing for reconfigurable multimedia processing are presented.
