is the circuit diagram of the initialization module which uses a +5V DC power supply. The figure shows four relays J00, J01, J10, J11 in the first two rows and the first two columns of the relayarray. The output port of the operational amplifier, Vout, is connected to the I/O port of FPGA, and the level characteristic of the I/O port is set to LVCMOS 3.3V. When the relay is closed, the resistance effect is ignored, the voltage of the non-inverting input terminal and the inverting input terminal of the operational amplifier are equal, the output voltage Vout is equal to 0, and the I/O port of the FPGA is detected as a low level. When the relay is disconnected, the voltage of the non-inverting input terminal of the operational amplifier is 1.647V and the inverting input terminal is grounded through R4 and R5 and connected with the output terminal through R7. We calculate that Vout is equal to 3.294V at this time, and the I/O port of the FPGA is detected as high level. After the FPGA receives the initialization command, it closes the corresponding relay. For the initialization of a single relay, the I/O port connected to Vout is "1" when the relay is disconnected, and Vout is "0" when the relay is closed. A detection level error indicates that the relay cannot be normally switched or the resistance is abnormal. For a faulty relay, the FPGA sends an error message and the corresponding relay number to the host computer.