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1: n-channel UFET Transistors for the 3nm node

1: n-channel UFET Transistors for the 3nm node

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Figure 0.2: n-channel and p-channel UFET connected as inverters
Figure 0.4: VTC and transistor's current flowing at two different Wp
Figure 0.5: VTC and currents in the n-UFET and p-UFET respectively
Figure 0.6: The Noise Margin Level of the UFET CMOS inverters
+77 Figure 0.7: VTC characteristics of inverters with reduced voltage levels
Design of a Novel Transistor Architecture for the Modern Sub-14nm ULSI Era
Thesis
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  • Jun 2015
This thesis dissertation is a study of scaled-down Field Effect Transistors prospect and new design of the Transistors configuration to continue Moore‘s law for sub 10nm node. Scaling down of the device size in an integrated circuit has enabled high-speed operation and miniaturization in size. However, scaling down the transistors beyond sub-10 nm...
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