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This paper focuses on the conversion gain (CG) of pixels implementing pinned photo-diodes (PPD) and in-pixel voltage follower in standard CMOS image sensor (CIS) process. An overview of the CG expression and its impact on the noise performance of the CIS readout chain is presented. CG enhancement techniques involving process refinements and pure ci...
Contexts in source publication
Context 1
... the SF drain to 1.5 V in order to accommodate the 1.8 V transistor to the 3.3 V environment. On the layout side, the introduction of a private n-well for the PMOS SF faces additional design rules constraints reducing the pixel fill factor. Indeed a minimum spacing needs to be respected between the PPD well and the PMOS n-well as shown in Fig. 7. On the other hand the SF gate width and length can be reduced to a value as low as 0.2 µm. In this pixel, a thinner metal wiring between the SN and the SF gate is also used in order to reduce the wiring parasitic capacitance with respect to the pixel variant previously introduced. With respect to the previous pixel variant, the fill ...
Context 2
... the SF drain to 1.5 V in order to accommodate the 1.8 V transistor to the 3.3 V environment. On the layout side, the introduction of a private n-well for the PMOS SF faces additional design rules constraints reducing the pixel fill factor. Indeed a minimum spacing needs to be respected between the PPD well and the PMOS n-well as shown in Fig. 7. On the other hand the SF gate width and length can be reduced to a value as low as 0.2 µm. In this pixel, a thinner metal wiring between the SN and the SF gate is also used in order to reduce the wiring parasitic capacitance with respect to the pixel variant previously introduced. With respect to the previous pixel variant, the fill ...
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