Fig 6 - uploaded by An-Yeu Wu
Content may be subject to copyright.
Source publication
Polar modulation techniques offer the capability of multimode wireless system and the potential for the high efficiency Power Amplifier (PA). This paper describes a new design of Digital Signal Processing (DSP) engine for the polar transmitter. The digital part includes rectangular-to-polar converter and digital phase modulator, and the engine is d...
Contexts in source publication
Context 1
... proposed DSP engine was implemented in UMC 0.18 um CMOS process with 1P6M technology. The layout of the DSP engine is shown in Fig. 6. The summary of the circuit is list in Table 3. 3.92 ...
Context 2
... propose a traceback architecture to reduce more SMM size. In our approach, The B k s are traced back with the forward recursions. The B k s of length L are generated in the backward recursion and then traced back in the trace-back recursion when A k s are generated. The trellis evolution of backward recursion and trace-back recursion is shown in Fig. 6 and the scheduling of this architecture is illustrated in Fig. ...
Similar publications
Aiming at the failure problems of integrated circuit (IC) caused by higher package density, thinner package, and more heat sources, taking a multichip module (MCM) for receiver front end as an example, the 3-D model is established based on ANSYS Parametric Design Language (APDL). Then, the steady-state thermal analysis is achieved to complete the a...
Recently, programmable metasurfaces have aroused great attention for various applications such as beam manipulation, wireless communication, and holograms by modulating the spatial phase or amplitude. However, programmable amplitude‐coding modulations have rarely been investigated due to the difficulty in realizing dynamic control of amplitude. Her...
A compact 60GHz power amplifier chip in 65nm CMOS technology of three-stage common source structure is presented. The first two amplifiers offer sufficient gain to pre-amplify the small input power. The third stage amplifier uses two sets of differential pairs to achieve power synthesis. On-chip transformer coupling is adopted to realize inter-stag...
This paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN...
![Schematic of the 300 GHz signal source[⁶⁶]](publication/361144828/figure/fig2/AS:11431281173713727@1689014078867/Schematic-of-the-300GHz-signal-source_Q320.jpg)
With the increasing number of users and emerging new applications, the demand for mobile data traffic is growing rapidly. The limited spectrum resources of the traditional microwave and millimeter‐wave frequency bands can no longer support the future wireless communication systems with higher system capacity and data throughput. The terahertz (THz)...
Citations
... When the required number of iterations have been completed the angle register z contains an approximation to atan2(x,y). The CORDIC algorithm does not converge for input angles |θ | > 90 0 , in order to support the full range of input angles the computation is decomposed into three stages [15]. First, a course angle rotation is performed to map the input argument into quadrant 1, next N micro rotations (using the CORDIC algorithm) are performed, and finally a quadrant correction is applied to account for the coarse angle rotation. ...
The necessity of high data rates wireless communication becomes important for the end-user, especially to support high mobility lifestyle "always get connected", and demand for the multimedia communication, such as the video phone, live streaming, online gaming, and the Internet. Since wireless communication systems need to deal with multiband and multimode operations on complex signals many-a-times, the efficient phase and magnitude extraction is always needed. This paper presents an architecture for the efficient rectangular to polar conversion (RPC) for these multiband and multimode wireless communications using fully parallel CORDIC, a Linear Convergence Algorithm. The architecture was synthesized with ISE 10. 1 software and was implemented in a Xilinx FPGA device achieving better performance than the previous LUT-based approaches.
... When the required number of iterations have been completed the angle register z contains an approximation to atan2(x,y). The CORDIC algorithm does not converge for input angles |θ | > 90 0 , in order to support the full range of input angles the computation is decomposed into three stages [14]. First, a course angle rotation is performed to map the input argument into quadrant 1, next N micro rotations (using the CORDIC algorithm) are performed, and finally a quadrant correction is applied to account for the coarse angle rotation. ...
In recent years, the growth of multimedia services and applications in digital data transmission has led to ever increasing demands of effective data transmission over the wired as well as wireless communication systems. Since digital communication systems need to deal with multimode and multiband operations on complex signals many-a-times, there is always a requirement of an efficient method for rapid phase and magnitude extraction. The proposed Rectangular to Polar Converter (RPC) has been implemented using fully parallel CORDIC, a Linear Convergence Algorithm, in vectoring mode. The design is synthesized with ISE 10.1 software, and implemented on 2v3000fg676-4. Synthesis results show that the design is able to work at 177.620 MHz with less hardware requirements. General Terms A rectangular to polar conversion is required so that transmitters must accommodate constant envelop signals as well as non-constant envelop signals to achieve multimode and multiband operations. In burst-mode communication systems, a rapid carrier is crucial. Hence a fast rectangular-to-polar conversion is needed. Delay-matching of phase as well as amplitude is crucial so that the restoration of the transmitted data at the receiver may be not be imperfect if the delays are unmatched.
This paper presents several architectural designs of rectangular-to-polar coordinate conversion (RPC) for digital communication systems. Given a two-dimensional (2-D) vector (x, y) , the key operation in the RPC is to calculate the arctangent value φ = tan-1( y / x) and the vector length ρ = √x2 + y2. We propose three multi-stage architectures for the design of the RPC, targeting for different precision requirements. The RPC operation can be considered as finding a rotation to align the given vector along the x axis. Such a rotation can be decomposed into three sub-rotations, each implemented by ROM-based multiplication-addition, linear approximation, or CORDIC micro-rotations. The major design consideration is how to partition the rotation angle and how to choose the proper architecture to minimize the total area cost. Implementation results show that the best architectural design is highly depends on the precision requirement.
A novel architecture to realize the conversion of rectangular to polar coordinates is presented in this paper. The proposed technique for phase calculation uses a logarithmic number system and does not require any multiplications, but only a few small tables and a few multi-operand additions. The modulus is computed by a constant multiplier, a lookup table, and a full multiplier. A test chip has been designed and fabricated in 0.25 mum CMOS. The realized circuit uses a novel high-speed modified double-pass transistor (DPL) full-adder cell to improve performance. The test chip includes two processors. The first one computes only the phase and reaches 482 MHz maximum clock frequency, with 0.37 mW/MHz power dissipation. The second processor computes the phase and modulus and works up to 430 MHz, with 0.64 mW/MHz. The experimental results compare favorably with previously reported architectures.
