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depicts the 1kbyte×8-bit non-imprinting SRAM array and the associated peripheral circuits such as row decoder, column decoder, input buffer, and sense amplifier. The SRAM array is arranged to be 32*32*8-bit architecture. The row decoder and column decoder decodes the 10-bit Address to triggers the word-line, WL to look for the designated SRAM cells in the array. The input buffer accepts the 8-bit Inputs to performs write operation to the designated SRAM cells if the Write signal is triggered. The sense amplifier performs read operation from the designated SRAM cells and amplifies the copied data to generate the 8-bit Outputs if the Read signal is triggered.
Source publication
We propose an dynamic-voltage-scaling (DVS) non-imprinting Master-Slave SRAM with high speed erase, for low power high secured defense applications. There are three key features in the proposed design. First, the stored data is periodically toggling in the SRAM cell to prevent data imprint, hence our design is highly secured against the unauthorize...
Contexts in source publication
Context 1
... operation to the designated SRAM cells if the Write signal is triggered. The sense amplifier performs read operation from the designated SRAM cells and amplifies the copied data to generate the 8-bit Outputs if the Read signal is triggered. Fig. 4 depicts the non-imprinting SRAM cell, which is used to build the 32*32*8-bit SRAM array (in the Fig. 3). The proposed SRAM comprises a reset circuit, a master circuit, a slave circuit, a clock tree and a read/write circuit. The reset circuit performs the high speed erase operation of the stored data when Rst is triggered. The master circuit inverts the data from S to Q when Clk 2 is triggered. The slave circuit copies the data from Q to ...
Context 2
... buffer, and sense amplifier. The SRAM array is arranged to be 32*32*8-bit architecture. The row decoder and column decoder decodes the 10-bit Address to triggers the word-line, WL to look for the designated SRAM cells in the array. The input buffer accepts the 8-bit Inputs to performs write operation to the designated SRAM cells if the Write signal is triggered. The sense amplifier performs read operation from the designated SRAM cells and amplifies the copied data to generate the 8-bit Outputs if the Read signal is triggered. Fig. 4 depicts the non-imprinting SRAM cell, which is used to build the 32*32*8-bit SRAM array (in the Fig. 3). The proposed SRAM comprises a reset circuit, a master circuit, a slave circuit, a clock tree and a read/write circuit. The reset circuit performs the high speed erase operation of the stored data when Rst is triggered. The master circuit inverts the data from S to Q when Clk 2 is triggered. The slave circuit copies the data from Q to S when Clk 1 is triggered. Clk 1 and Clk 2 are the non-overlapping clocks generated by the Toggling_Clk 1 and Toggling_Clk 2 from the system via a series of clock tree. The clock tree is to maintain the signal strength for high number of fan-outs in the overall 1kbyte×8-bit SRAM ...
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Spin-Transfer Torque RAM (STTRAM) is promising for cache applications. However, it brings new data security issues that were absent in volatile memory counterparts such as Static RAM (SRAM). This is primarily due to the fundamental dependency of this memory technology on ambient parameters such as magnetic field and temperature that can be exploite...
Citations
... However, to feature the non-imprinting and high-speed erase mechanisms, the reported NIHE 22-T SRAM cell [5], [9] occupies a comparatively larger area overhead. The large overhead also leads to high power dissipation (with significant amount of leakage power). ...
... A [9] MT_CLK ST_CLK T_RST ...
Protecting user’s secret data on the devices like smartphones, tablets, wearable devices etc, from memory attacks is always a challenge for system designers. The most stringent security requirements and protocols in today’s state-of-the-art systems are governed by Federal Information Processing Standards (FIPS). Specifically, it ensures the protection of sensitive data by erasing them from random access memories (RAMs) and associated flip-flip based registers, as soon as security violation(s) is(are) detected. Traditionally, the sensitive data like authentication credentials, cryptographic keys and other on-chip secrets are erased (or zeroized) by sequential write transactions initiated either by dedicated hardware or using software programs. This paper, for the first time, proposes a novel approach of erasing secured data content from on-chip RAMs using conventional memory built-in-self-test (MBIST) hardware in mission mode. The proposed zeroization approach is proved to be substantially faster than the traditional techniques in erasing data content. As it helps in re-using Memory BIST hardware for on-chip data content zeroization, this guarantees to save silicon area and power by removing dedicated conventional hardware from the device. This paper also discusses the micro-architectural implementation and security challenges of using Memory BIST hardware in mission mode and proposes practical solutions to fill the gaps.
We study the security feature of static random access memory (SRAM) against the data imprinting attack and provide a solution to protect the SRAM from this attack. There are four main contributions in this paper. First, the negative-bias temperature-instability (NBTI) degradation of PMOS transistors in the conventional SRAM cell that causes the data imprinting effect is explained. Second, the data imprinting effect that leaks the stored information in the conventional SRAM cell is investigated. Third, a novel low transistor-count transmission-gate-based master-slave SRAM cell is proposed to periodically toggle the stored data for reducing the data imprinting effect. Fourth, an efficient imprinting analysis flow is proposed to evaluate the proposed data-toggling SRAM for quantifying the data imprinting effect. Based on a 65-nm CMOS process, we implement and prototype the proposed 1k-byte data-toggling SRAM design. We perform our imprinting analysis flow on various SRAM ICs and benchmark our proposed data-toggling SRAM IC against the non-toggling SRAM IC and a commercial Lyontek SRAM IC. From the measurement results, the non-toggling SRAM and Lyontek SRAM suffer from 60% and 81% data imprinting effects, respectively, whereas our data-toggling SRAM has only 11% data imprinting effect (at 160-kHz toggling frequency). The data-toggling SRAM could switch between high security (<5% data imprinting effect) high power mode for hardware security applications and low power (<0.1mW) low security mode for power-saving applications. Particularly, our data-toggling SRAM could feature as low as ~1% data imprinting effect when increasing the toggling frequency to 1.6 MHz by compromising the power dissipation. Using the image analysis flow, the stored information is revealed in both the non-toggling and Lyontek SRAM ICs but is well protected in the proposed data-toggling SRAM IC.
Protection of secured data content in volatile memories (processor caches, embedded RAMs etc) is essential in networking, wireless, automotive and other embedded secure applications. It is utmost important to protect secret data, like authentication credentials, cryptographic keys etc., stored over volatile memories which can be hacked during normal device operations. Several security attacks like cold boot, disclosure attack, data remanence, physical attack, cache attack etc. can extract the cryptographic keys or secure data from volatile memories of the system. The content protection of memory is typically done by assuring data deletion in minimum possible time to minimize data remanence effects. In today's state-of-the-art SoCs, dedicated hardwares are used to functionally erase the private memory contents in case of security violations. This paper, in general, proposes a novel approach of using existing memory built-in-self-test (MBIST) hardware to zeroize (initialize memory to all zeros) on-chip memory contents before it is being hacked either through different side channels or secuirty attacks. Our results show that the proposed MBIST based content zeroization approach is substantially faster than conventional techniques. By adopting the proposed approach, functional hardware requirement for memory zeroization can be waived.
