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![d: Peres (PG) gate [12]](profile/Geetha-Priya-m/publication/258991132/figure/fig4/AS:340567893528581@1458209121795/d-Peres-PG-gate-12.png)
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![Fig. 1c: Fredkin (FRG) gate [11]](profile/Geetha-Priya-m/publication/258991132/figure/fig3/AS:340567893528580@1458209121769/c-Fredkin-FRG-gate-11_Q320.jpg)
![Fig. 1d: Peres (PG) gate [12]](profile/Geetha-Priya-m/publication/258991132/figure/fig4/AS:340567893528581@1458209121795/d-Peres-PG-gate-12_Q320.jpg)
![Fig. 1a: Feynman (FG) gate [9]](profile/Geetha-Priya-m/publication/258991132/figure/fig1/AS:340567893528578@1458209121714/a-Feynman-FG-gate-9_Q320.jpg)
![Fig. 1b: Toffoli (TG) gate [10]](profile/Geetha-Priya-m/publication/258991132/figure/fig2/AS:340567893528579@1458209121741/b-Toffoli-TG-gate-10_Q320.jpg)
![Fig. 1e: BVF gate [13] Existing Reversible Wallace Tree Multiplier: The...](profile/Geetha-Priya-m/publication/258991132/figure/fig5/AS:340567893528582@1458209121815/e-BVF-gate-13-Existing-Reversible-Wallace-Tree-Multiplier-The-existing-design-for-8X8_Q320.jpg)
Reversible logic gates provide power optimization which can be used in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a Novel reversible 4:2 compressor, 6:2 compressor and 9:2 compressor designed from the DKGP gate that can work singly as a reversible full adder/full subtractor. These are later u...
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Reversible logic is an important area to carry the computation into the world of quantum computing. In thispaper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate isa 5 x 5 reversible gate which is designed to generate partial products required to perform multiplicationand also duplication of operand bi...
Reversible logic in quantum computing and nanotechnology provides solution to optimize the power and this technology can be put into use in a variety of low power applications such as optical computing, and CMOS VLSI design. An EXNOR gate is a digital logic gate that can be used as an equivalence gate and also in variety of applications. A new reve...
In this paper, the introduction of basics reversible logic gates are used for reversible operation and also can be used for synchronous and asynchronous counter. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current sta...
Citations
... The BVF gate serves the purpose of extracting essential inputs to fulfill the fan-out requirements. Its block diagram is shown in Figure 24 [73]. ...
... This is the author's version which has not been fully edited and content may change prior to final publication. [71] A AB⊕C AD⊕C AB⊕C⊕D Pareek [72] A AB⊕AD AB⊕AD⊕C B⊕D SCL [73] A B C A(B+C)⊕D PPHCG [74] B⊕C⊕D A⊕B⊕C A⊕B⊕D A⊕C⊕D TSG [62] A A C⊕B (A C ⊕B)⊕D (A C ⊕B)D⊕(AB ⊕ D) PFAG [75] A A⊕B A⊕B⊕C (A⊕B)C⊕AB⊕D HNG [76] A B A⊕B⊕C (A⊕B)C⊕AB⊕D PAOG [77] A A⊕B AB⊕D ((A⊕B)⊕D)⊕(AB⊕C) MRG [77] A A⊕B (A⊕B)⊕C (AB⊕D)⊕((A⊕B)⊕C) SMS [78] A⊕C⊕D D⊕BC C D⊕B⊕C⊕BC RI [79] A⊕C B⊕C⊕AB⊕BC A⊕B⊕C D⊕C⊕AB⊕BC OTG [80] A A⊕B A⊕B⊕D (A⊕B)D⊕(AB⊕C) MCT [63] A B C ABC⊕D DKG [81] B AC+AD (A⊕B)(C⊕D)⊕CD B⊕C⊕D SG [82] A AB⊕AC AB⊕AC⊕D AB⊕AC⊕D MRLG [83] A AB⊕AC B⊕AC B⊕AC⊕D RAM [84] A A⊕B A⊕B⊕C A⊕B⊕C⊕D HNFG [85] A A⊕C B B⊕D FAS [54] A⊕B⊕C (B⊕C⊕D)A⊕(C⊕D)B C B⊕C⊕D BVF [86] A A⊕B C C⊕D MKG [87] A ...
The reversible gate has been one of the emerging research areas that ensure a continual process of innovation trends that explore and utilizes the resources. This review paper provides a comprehensive overview of reversible gates, including their fundamental principles, design methodologies, and various applications. It also analyzes the reversible gates, comparing them based on metrics such as Quantum Cost, Complexity, and other performance evaluation measures. The analysis of several reversible gates is presented in this paper and provides a comprehensive overview of reversible gates, encompassing their fundamental principles, design methodologies, and diverse applications. Reversible logic circuits allow for the production of both unique outputs and distinct input combinations. The majority of the findings about the reversible gates from previous research papers are discussed and contrasted. All the reversible gates that have been proposed till now are presented in tabular form and the parameters are discussed to help the researchers to find every detail related to the reversible gates. To highlight our understanding, we have ended most of the sections with questions. The inclusion of questions is likely intended to stimulate further discussion and promote a deeper understanding of the material presented in this paper. These questions can serve as prompts for readers to reflect on the content and potentially explore related research directions or areas of improvement.
... Many reversible logic gates are available in the literature out of which few are Feynman gate (FG) [6] also called as CNOT gate, Toffoli gate (TG) [7] or C 2 NOT gate, Fredkin gate (FRG) [8], Peres gate (PG) [9], PFAG [10], HNG [11], TSG [12], DKG [13], DKGP [14], SRK [15], SV [16] and CIIRC gate [17]. ...
The technique of reversible logic can be applied on any digital, VLSI and quantum computing applications for optimization of power. A decoder and an encoder are the basic building blocks that can be used to realize any logic network. This pair can be used in communication system applications as transceivers. A new 4 × 4 reversible gate named FADE is proposed in this paper which is novel, unique and first of its kind as it performs the operation of three combinational logic circuits simultaneously, i.e., a full adder, a 2:4 decoder and a 4:2 encoder simultaneously. The design of the proposed reversible gate is coded using Verilog, synthesized and simulated using Xilinx software. It is implemented and tested on FPGA XC3S400-5PQ208. This gate would act as a threshold in designing complex arithmetic logic circuits and thus enhance the performance of computing systems.
... NOR gate output cannot be realized. Quantum cost, garbage outputs, reversible logic gates used and constant inputs are 17, 1, 1 and 2 respectively.. • DKGP gate [21] is used to realize Copy, NOT, EXOR, AND, OR and NOR gates using two control signals. Same constant inputs do not produce all basic gate or universal gate outputs simultaneously. ...
Optimization of device power can be achieved using reversible logic computation and this technique can be applied to a variety of low power applications such as optical computing, nanotechnology, Complementary Metal Oxide Semiconductor (CMOS) Very Large-Scale Integrated Circuits (VLSI) design and many more. Basic and universal gates are the basic building blocks of digital system. In this paper, a new reversible Basic, Universal and Special (BUS) gate is proposed that is available as a single gate with multiple functionalities as basic (AND, OR & NOT), universal (NAND & NOR) and special gate (EXOR). The proposed BUS gate is implemented on Field Programmable Gate Array (FPGA) and simulated using 180nm and 90nm CMOS process technologies. Manchester adder and C17 circuit of ISCAS'85 (International Symposium on Circuits and Systems-1985) benchmark suite using BUS gate are designed and verified using Electronic Design Automation (EDA) tools. There is a power reduction of about 64.41% and 14.06% at 180nm and 90nm CMOS process technologies respectively in reversible BUS gate as compared to conventional CMOS-based designs. Thus, this paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems with low power dissipation.
... A few of the numerous reversible gates that are available in literature are highlighted in this section with respect to quantum cost, input and output vectors and are listed in Table 1. Few other Reversible logic gates available are TG (Toffoli), FRG (Fredkin) [3], DKGP [4]. ...
Reversible logic in quantum computing and nanotechnology provides solution to optimize the power and this technology can be put into use in a variety of low power applications such as optical computing, and CMOS VLSI design. An EXNOR gate is a digital logic gate that can be used as an equivalence gate and also in variety of applications. A new reversible SV gate is proposed in this paper that functions as an EXNOR gate and whose quantum cost is 1. An equivalence checker also has been designed in this paper that can be used to check the equivalence of two n-bit binary numbers. The proposed SV gate has been validated by comparing its performance with some of the existing circuits in literature. The results prove to be more reliable, efficient and provide a basis for building more complex arithmetic systems using the concept of reversible logic that can be used in digital data transmission circuits.
... In [27], 4-2 compressors and designed using new HNG/RFA gate. This is proven to be the fastest among the compressor designs in conventional CMOS implementation in terms of delay, logic depth and power [17]. ...
Compressors play a specific role in realizing high-speed arithmetic circuits in particular multipliers. The increase in the demand of fast multiplication has attracted many researchers to design higher order compressors which enhance the speed of computation by reducing the critical path delay of the processing unit. In this paper, quantum cost and delay-optimized compressors are proposed. The compressors are designed using existing reversible gates such as Feynman, Fredkin, and Peres gates (PG). Using these optimized compressors, 8 × 8 Wallace multiplier is designed and the performance parameters are compared with the existing designs in the literature. It is evident from the results that this design exhibits better performance parameters and lesser delay and hence it is faster compared to existing designs in the literature. Thus, this design is suitable for high-speed arithmetic circuits such as FFTs, IFTs in modern DSP design.
... A 4* 4 reversible DKG gate [6] that can work singly as a reversible Full adder and a reversible Full subtractor is shown inFig 1a. It can be verified that input pattern corresponding to a particular output pattern can be uniquely determined. ...
Under ideal conditions, Reversible logic gates produce zero power dissipation. So these can be used for low power VLSI design. This paper proposes a new reversible parallel adder/subtractor using 4*4 Reversible DKG gate that can work singly as a reversible full adder and a full subtractor. A serial adder/subtractor is also designed in this paper using Reversible Universal Shift registers and DKG gate.This paper provides a threshold to build more complex arithmetic systems using reversible logic.
Reversible adders are essential circuits in quantum computing systems. They are a fundamental part of the algorithms implemented for such systems, where Shor's celebrated factoring algorithm is one of the most prominent examples in which reversible arithmetic is needed. There is a wide variety of works in the existing literature which tackle the design of an adder for quantum systems, and today there is still a great interest in the creation of new designs and the perfection of the existing ones. Similar to how it happens in classical digital systems, there are different methodologies to approach the addition using reversible circuits. Some methodologies focus on minimizing the necessary resources, others on optimizing computing time, etc. In this work we analyze the reversible adders in the state-of-the-art for quantum computing, classifying them according to their type, and finally, comparing each other using referenced and validated metrics that allow highlighting the strengths and weaknesses of each adder.
A low power reversible 8-bit ALU using single electron transistor (SET) for Nano processors is designed in this paper. Since there is a possibility in reversible logic to build circuits from many-port gates that do not destroy the capacity to store information, the basic blocks of ALU are constructed using one of the assuring many port gates called DKGP reversible gate. Then the blocks are technologically advanced to the transistor level using CMOS technology. The outputs are verified for given input frequency with the operating voltage of 5 V using SPICE simulation. It is also observed that the output glitches are obtained with low operating voltage of less than 2 V in CMOS technology. The same blocks of ALU are constructed using SET technology and the outputs are verified through simulation. The simulation results have shown that the same output response with no glitches is obtained for the same input frequency as in CMOS, with very low operating voltage of 25 mV. It is inferred that there is a drastic difference in power dissipation with SET and CMOS technology. Therefore SET technology has the potential toward the development of Nano-electronic components and can be adopted for various low power digital applications. This is the first attempt to design reversible ALU using pure SET technology from our study.
