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Security threats are affecting the evolution in cryptographic algorithms, and modular arithmetic is an important part of these algorithms, especially in the case of public-key cryptosystems. To obtain optimal system performance and not to lose physical security, it is desirable to implement cryptographic algorithms in hardware. However, many public...
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Modular reduction of large values is a core operation in most common public-key cryptosystems that involves intensive computations in finite fields. Within such schemes, efficiency is a critical issue for the effectiveness of practical implementation of modular reduction. Recently, Residue Number Systems have drawn attention in cryptography applica...
Citations
This paper implements a Brent–Kung adder design from register-transfer level (RTL) to Graphic Database System Information Interchange (GDSII), using Cadence Genus and Innovus tools. Brent–Kung Adder is selected with a 16-bit word size as it is considered suitable for very large-scale integration (VLSI) implementation out of the other parallel prefix adder implementation. It is provided with scan chain flip-flops which cover the overall design. This design has been implemented at 180 and 45 nm technology nodes. The design was optimized as per trade-offs between area, delay, and power. The power dissipation observed for 45 nm is 26.7 µW, 0.03 ns critical path delay with 413.136 µm2 area taken up. It adheres to scalability by providing better performance metrics at 45 nm than the 180 nm technology node. For this particular implementation, the main highlight is the power consumption and the speed of the implementation, as we have illustrated below via comparison with other works through tabular means.
