Fig 3 - uploaded by Peter Ossieur
Content may be subject to copyright.
Source publication
![Fig. 2 GPON burst-mode laser driver stage [3].](profile/Peter-Ossieur/publication/31225740/figure/fig2/AS:339780232597507@1458021328159/GPON-burst-mode-laser-driver-stage-3_Q320.jpg)
This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 μm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differentia...
Contexts in source publication
Context 1
... because the output capaci- tance of the IDAC would reduce the output impedance at higher frequencies and deteriorate the current switching be- havior of the laser driver. A cascade transistor could solve this problem but the extra voltage drop cannot be tolerated. So the IDAC currents are transferred to the differential pairs via current mirrors (Fig. 3) optimized for speed and power consumption, to not deteriorate the IDAC settling ...
Context 2
... architecture of the IDAC is shown in Fig. 3 and a switching scheme is proposed for fast settling and low glitch energy. Basically, it is a 10-bit segmented architec- ture that has been implemented with a 4-bit unit-element sub-DAC and a 6-bit binary-weighted sub-DAC. The seg- mented current-steering topology was chosen for a high monotony. To be compatible with the laser driver ...
Context 3
... sub-DAC and a 6-bit binary-weighted sub-DAC. The seg- mented current-steering topology was chosen for a high monotony. To be compatible with the laser driver archi- tecture [3] (Fig. 2), the IDAC must sink the current into 8 identical fast NPN current mirrors which build the IDAC output stage. The segmented current steering architecture of Fig. 3 shows 16 segment current sources (I 0 to I 15 ) and 6 weighted current sources. The currents are switched to 8 output current mirrors (Mirror 0 to Mirror 7) (to be dis- cussed in Sect. 5) to be compatible with the laser driver ar- chitecture [3]. Eight unity-gain voltage buffers (to be dis- cussed in Sect. 4) acting as the dummy ...
Context 4
... cussed in Sect. 4) acting as the dummy mirrors which make the voltage at the negative current output of IDAC equal to the voltage at the positive current output. A small current (5 µA) is added to the input of the output current mirrors as a pre-bias current which can increase the settling time of this mirror considerably. I OUT0 to I OUT7 in Fig. 3 are the same currents as in Fig. 2, which represents the current amplified by a 1:12 cur- rent mirror. Every segment current from I 0 to I 15 (437.5 µA) is generated by a high-swing low-voltage cascade PMOS current mirror, made up of 64 unit current sources I UNIT . Switching the 6-bit LSBs (Least Significant Bits) sub-DAC from segment ...
Similar publications
The importance of within-die process variation and its impact on product yield has increased significantly with scaling. Within-die variation is typically monitored by embedding characterization circuits in product chips. In this work, we propose a minimally-invasive, low-overhead technique for characterizing within-die variation. The proposed tech...
Voltage Fault Injection (VFI), also known as power glitching, has proven to be a severe threat to real-world systems. In VFI attacks, the adversary disturbs the power-supply of the target-device forcing the device to illegitimate behavior. Various countermeasures have been proposed to address different types of fault injection attacks at different...
In order to ensure good charging performance of new energy vehicles, the charging station was designed and the relevant oscillation circuits were optimized. The function and structure of the charging station was determined, and through a hierarchical framework, not only the success rate factor could be corrected, but also a resonant converter was c...
Designing LSI chips has proven to be a big challenge. Parameter-process, voltage, temperature, and aging-variations have increased and hence circuit delays are no longer deterministic. Applications working in harsh environments are emerging and continuous power supply sometimes becomes difficult. Furthermore, such a demand of much lower power consu...
Citations
... The Least gigantic Bit (LSB) actuates little plentifulness framework imperfections as background noise the recurrence zone 6 . An excessive number of portioned stages can amplify the computerized clamor and worsen the effectiveness 8 . The static effectivity of DACs reminiscent of DNL and INL must be considered, also because the dynamic execution of DACs likes SFDR. ...
Aim / Objective: The (24, 12) binary Golay code was a well-established rate-1/2 short block-length linear error detecting and
correcting code with High performance.
Algorithm / Simulation: This paper investigates the design of an efficient low-complexity soft-decision decoding architecture
for this Golay code. A new algorithm is introduced that takes a huge advantage of the code’s properties to reduce and simplify
the decoding process.
Findings & Results: The Simulation result shows that the proposed algorithm of Modified soft decision decoding achieves high
performance rates with low processing cost. Here the decoder architecture is mentioned, and VLSI synthesis results are
presented.
Applications: can be used in high speed cryptography systems
... The LSB introduces small amplitude glitches as white noise in the frequency domain [6]. Too many segmented stages can increase the digital noise and worsen the performance [8]. ...
A low-voltage low-power small-area digital to analog converter (DAC) for high speed applications is introduced in this paper. A current steering digital to analog converter is well suitable for high speed application, because all the currents taken from the supply is used for the output signal. In this paper it deals with the design and analysis of an 8-bit current steering digital to analog converter which was implemented using full Swing (FS) GDI Logic in CMOS process. The active area of this proposed DAC was reduced to four times in a standard 1P3M 0.13 µm 3.3V CMOS process, both the INL and DNL were reduced to half of 8-bit DAC implemented using conventional logic gates.
... Very interesting segmented architectures of current-steering digital-to-analog converters were presented in [2], [5] and [6], but there the dynamic randomization is made at most inside each segment of the code because the current sources are not identical over the segments. Typically, the fullrandomization techniques are used in lower-bit DACs and for example in the feedback DACs in sigma-delta ADCs [2], [4]. ...
In this paper we aim to optimize the splitting of the input control code of a current-steering segmented digital-to-analog converter which uses identical unit current sources only. Both matching error and area are taken into discussion to analyze the static and dynamic performances of the converter. Power consumption considerations are presented and the final optimized code segmentation will be offered for a 10-b 0.35-μm CMOS DAC included in a sub-bandgap mechanism.
In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight.The digital-to-analog converter was implemented using TSMC 0.35 μm, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm2.The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application.
In this paper we present an optimized structure of a 10-b current-steering digital-to-analog converter (DAC) with very good dynamic performance, especially regarding spurious-free dynamic range (SFDR). To reduce the influence of matching errors, an appropriate dynamic element matching (DEM) technique was implemented and OrCAD simulations were used to confirm more realistic improvements than in related works.
