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In the systems on chip (SoC) design, the synthesis of communication architecture constitutes the bottleneck which can affect the performances of the system. Various schemes and protocols can be necessary, just as various topologies of interconnection. To reduce the complexity of the communications refinement, we present in this study a model and a...
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... components which have the same value of the function H(I, J) have the same set of priorities. The Fig. 4b, shows an example of a communication graph for the hypothetical architecture of the Fig. 4a. ...
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... the two metric ones for the busj. For each bus, the highest priority is assigned with the component which have the greatest value of the function H(I, J). The components which have the same value of the function H(I, J) have the same set of priorities. The Fig. 4b, shows an example of a communication graph for the hypothetical architecture of the Fig. ...
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... procedure. The output of this procedure is a VHDL description Multibus_VHDL_Description which will be integrated in the communication bridge. The details of VHDL descriptions of different sub-modules from arbitration as well as the technique of RTL synthesis are presented [12] . The method of instantiation in the case of system of Fig. 4a is presented as ...
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Citations
... Several specific direct uses of FSMs in security critical hardware include anti-lock brake systems, [5] pacemakers [6] and other medical devices [7]. Beyond these computational lightweight devices, FSMs are often used in the development of the communication protocols between reusable IPblocks and core security and orchestration blocks in Systems-on-Chip [8,9]. To alleviate this weakness, a high-level method described in [10] eliminates the relationship between FSMs and side channel models. ...
... Thus, given an n-bit encoding (n ≤ s), each of the s states should have c bits on and n − c bits off. Selection of n and c must satisfy (9) to insure all the states can be represented uniquely. Furthermore, to minimise power consumption c should satisfy (10). ...
Security‐centric components and systems, such as System‐on‐Chip early‐boot communication protocols and ultra‐specific lightweight devices, require a departure from minimalist design constructs. The need for built‐in protection mechanisms, at all levels of design, is paramount to providing cost‐effective, efficient, secure systems. In this work, Securely derived Finite State Machines (S*FSM) and power‐aware S*FSM are proposed and studied. Overall results show that to provide an S*FSM, the typical FSM requires a 50% increase in the number of states and a 57% increase in the number of product terms needed to define the state transitions. These increases translate to a minimum encoding space increase of 70%, raising the average encoding length from 4.8 bits to 7.9 bits. When factoring in relaxed structural constraints for power and space mitigation, the respective increases of 53 and 67% raise the average number of bits needed to 7.3 and 7.9. Regarding power savings, current minimisation is possible for both FSMs and S*FSMs through the addition of encoding constraints with average current reductions of 30 and 70%, respectively. Overall, a power‐constrained S*FSM consumes about 5% more power than insecure FSMs with binary encodings, though with a penalty of a 95% increase in layout area.
... An EFSM [29] is a transition system which allows a more compact and intuitive representation of the state space with respect to the traditional finite state machines (FSMs). The EFSM model is widely used for modeling complex systems like reactive systems [30], communication protocols [31], buses [32] and controllers driving data-path [33]. EFSM has been adopted in this work to easily represent communication protocols based on transactions as well as mutations on TLM code, as explained in Section 4. ...
Transaction-level modeling (TLM) has become the de-facto reference modeling style for system-level design and verification of embedded systems. It allows designers to implement high-level communication protocols for simulations up to 1000x faster than at RTL. To guarantee interoperability between TLM IP suppliers and users, designers implement the TLM communication protocols by relying on a reference standard, such as the standard OSCI for SystemC TLM. Functional correctness of such protocols as well as their compliance to the reference TLM standard are usually verified through user-defined testbenches, which high-quality and completeness play a key role for an efficient TLM design and verification flow. This article presents a methodology to apply mutation analysis, a technique applied in literature for SW testing, for measuring the testbench quality in verifying TLM protocols. In particular, the methodology aims at (i) qualifying the testbenches by considering both the TLM protocol correctness and their compliance to a defined standard (i.e., OSCI TLM), (ii) optimizing the simulation time during mutation analysis by avoiding mutation redundancies, and (iii) driving the designers in the testbench improvement. Experimental results on benchmarks of different complexity and architectural characteristics are reported to analyze the methodology applicability.
... Such a tool, namely, EGEN, automatically extracts EFSM models from HIF descriptions. EFSMs represent a compact way for modeling complex systems like, for example, communication protocols [17], buses [18], and controllers driving data-paths [19,20]. Moreover, they represent an effective alternative to the traditional finite state machines (FSMs) for limiting the state explosion problem during test pattern generation [21]. ...
HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and post-refinement verification.
... Such a tool, namely, EGEN, automatically extracts EFSM models from HIF descriptions. EFSMs represent a compact way for modeling complex systems like, for example, communication protocols [17], buses [18], and controllers driving data-paths [19] [20]. Moreover , they represent an effective alternative to the traditional finite state machines (FSMs) for limiting the state explosion problem during test pattern generation [21]. ...
... ( [17], buses [18], and controllers driving data-paths [19, 20] . Moreover , they represent an effective alternative to the traditional finite state machines (FSMs) for limiting the state explosion problem during test pattern generation [21]. ...
Abstract HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and postrefinement verification.
... . EFSM models of some SystemC TLM-2.0 primitives. used for modeling complex systems like reactive systems, communication protocols, buses and controllers driving datapath [11], [12]. 2) Classification of TLM primitives: In TLM-2.0, ...
... Given a transition out-going from a state, the transition is fired, bringing the machine from the current state to the next state and performing the operation included in the update function, once the conditions involved in the enabling function are all satisfied. The EFSM model is widely used for modeling complex systems like reactive systems, communication protocols, buses and controllers driving data- path [11], [12]. 2) Classification of TLM primitives: In TLM-2.0, ...
The topic will cover the use of functional qualification for measuring the quality of functional verification of TLM models. Functional qualification is based on the theory of mutation analysis but considers a mutation to have been killed only if a testcase fails. A mutation model of TLM behaviors is proposed to qualify a verification environment based on both testcases and assertions. The presentation describes at first the theoretic aspects of this topic and then it focuses on its application to real cases by using actual EDA tools, thus showing advantages and limitations of the application of mutation analysis to TLM.
... Given a transition out-going from a state, the transition is fired, bringing the machine from the current state to the next state and performing the operation included in the update function, once the conditions involved in the enabling function are all satisfied. The EFSM model is widely used for modeling complex systems like reactive systems [22], communication protocols [23], buses [24] and controllers driving data-path [25]. ...
Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Similar approaches are applied in hardware verification and testing too, especially at RTL or gate level, where mutants are generally referred as faults, and mutation analysis is performed by means of fault modeling and fault simulation. However, in modern embedded systems there is a close integration between HW and SW parts, and verification strategies should be applied early in the design flow. This requires the definition of new mutation analysis-based strategies that work at system level, where HW and SW functionalities are not partitioned yet. In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions. In particular, the main constructs provided by the SystemC TLM 2.0 library have been analyzed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.
... A good survey on co-design methodologies and frameworks can be found in [15]. Co-synthesis methodologies [16,17,18,19,20,21,22,23] is another step forward with abilities of auto-synthesizing high-level models into C code for software and HDL code for hardware. ...
... With the availability of various reusable IP cores, a same functional specification can be implemented by a broad range of computation and communication architectures which could result in several orders of magnitude difference in performance, power consumption, or chip area. Obviously, the conventional co-design methodologies have the laid the foundation for early hardware and software integration and evaluation, but their evaluation capacity are limited to a single or very few of design solutions derived 23 from processor-centered template architectures because they are lacking of fast and efficient design space exploration process and design alternative trade-off analysis. ...
With the advent of heterogeneous multiprocessor system-on-chips (MPSoCs), hardware/software partitioning is again on the rise both in research and in product development. In this new scenario, implementing intellectual-property (IP) blocks as SW applications rather than dedicated HWis an increasing trend to fully exploit the computation power provided by theMPSoC CPUs. On the other hand, whole libraries of IP blocks are available as RTL descriptions, most of them without a corresponding high-level SW implementation. In this context, this article presents a methodology to automatically generate SW applications in C++, by starting from existing RTL IPs implemented in hardware description language (HDL). The methodology exploits an abstraction algorithm to eliminate implementation details typical of HW descriptions (such as cycle-accurate functionality and data types) to guarantee relevant performance of the generated code. The experimental results show that, in many cases, the C++ code automatically generated in a few seconds with the proposed methodology is as efficient as the corresponding code manually implemented from scratch.
The multiprocessor SoC designs have more than one processor and huge memory on the same chip. SoC consists of hardware cores and software cores ,multiple processors, embedded DRAM and connectors between cores .A wide range of MPSOC architectures have been developed over the past decade. This paper surveys the history of various On-Chip communication architectures present in the design of MPSoC. This acts as a primary factor of overall performance in complex SoC designs. Some of the various techniques that have driven the design of MpSoC has been discussed. Dynamically configurable communication architectures are found to improve the system performance. Currently On-chip interconnection networks are mostly implemented using shared buses which are the most common medium. The arbitration plays a crucial role in determining performance of bus-based system, as it assigns priorities, with which processor is granted the access to the shared communication resources. In the conventional arbitration algorithms there are some drawbacks such as bus starvation problem and low system performance. The bus should provide each component a flexible and utmost share of on-chip communication bandwidth and should improve the latency in access of the shared bus. The performance of SoC is improved using the probabilistic round robin algorithm with regard to the parameters, latency.Thus in this paper various issues related to bus arbitration related to design of MPSoC is analysed.
Functional verification techniques based on fault injection and simulation at register-transfer level (RTL) have been largely investigated in the past years. Although they have various advantages such as scalability and simplicity, they commonly suffer from the low speed of the cycle-accurate RTL simulation. On the other hand, Transaction-level modeling (TLM) allows a simulation speed sensibly faster than RTL. This article presents FAST, a framework to accelerate RTL fault simulation through automatic RTL-to-TLM abstraction. FAST abstracts RTL models injected with any RTL fault model into equivalent injected TLM models thus allowing a very fast fault simulation at TLM level. The article also presents FAST-DT, a new bit-accurate data type library integrated in the framework that allows a further improvement of the simulation speed-up. Finally, the article shows how the generated TLM test patterns can be automatically synthesized into RTL test patterns by exploiting the structural information of the RTL model extracted during the abstraction process. Experimental results have been performed on several designs of different size and complexity to show the methodology effectiveness.
