(a)general circuit diagram of the wireless series-parallel inductive link (b) circuit diagram of the wireless link for our design.

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... power is available at two frequency splitting points [22], not at the resonant frequency. In this paper, we use the series-parallel resonance model to briefly illustrate the link characteristics of the frequency-splitting-based inductive coupling. A general circuit diagram of a series-parallel inductive link for the WPT system is shown in Fig. 1(a), where R L1 and R L2 are the parasitic resistances of inductors L 1 and L 2 respectively, and C 1 and C 2 are the resonant capacitors. When the coupling coefficient k=0, the resonant frequency ω 0 ...

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... make the link more realistic and conservatively estimate the link characteristics (especially the PTE), we consider the parasitic resistance of the power supply as well as the wires. The designed link model is shown in Fig. 1(b), where R s1 and R s2 are the parasitic resistances of the link respectively. The component parameters of the link are shown in Table 1. We simulated the characteristics of the designed link and the results are shown in Fig. 2. Fig. 2(a) shows the link gain curves with different loads R L . We choose the flat region of the link gain ...

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... The hysteresis voltage of the hysteresis comparator is designed to be larger than the output ripple of the envelope, which is important to reduce the BER of the demodulation [17]. Moreover, the appropriate loop bandwidth needs to be set in the circuit design to support high data rate demodulation without affecting the envelope output. As shown in Fig. 10 is the simulation result of the loop gain and phase bode diagram under the PVT variation, the feedback loop always satisfies phase margin (PM)>65° and the DC gain is greater than 54dB, which can maintain the frequency stability and closed-loop feedback accuracy over a wide range of input variations. This is essential for our ASK ...

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... proposed SWPDT system is implemented with the 180nm CMOS process. Fig. 11 shows a layout picture of the chip which occupies an area of 0.836mm 2 (0.88mm × 0.95mm). The performance of the proposed SWPDT system is verified by post-layout simulations. The simulations are carried out over a single inductive link with a coupling factor k of 0.2 (corresponding to a transmission distance of 1.45cm). The input ...

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... verify the performance and robustness of the active rectifier with adaptive delay compensation loops, the transient simulation results under different PVT corners are shown in Fig. 12 (a). With V REC =2V and R L =100Ω, both on-and off-delay eliminations are accomplished. M N 1 and M N 2 have maximum effective conduction time and there is no reverse current. Further, Fig. 12(b) shows the simulated PCE with Monte-Carlo mismatches. The delay compensation technique is also insensitive to mismatches and a high PCE of 94.1% ...

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... and robustness of the active rectifier with adaptive delay compensation loops, the transient simulation results under different PVT corners are shown in Fig. 12 (a). With V REC =2V and R L =100Ω, both on-and off-delay eliminations are accomplished. M N 1 and M N 2 have maximum effective conduction time and there is no reverse current. Further, Fig. 12(b) shows the simulated PCE with Monte-Carlo mismatches. The delay compensation technique is also insensitive to mismatches and a high PCE of 94.1% is achieved. Thus, the stability and feasibility of delay compensation are guaranteed. Meanwhile, the high PCE active rectifier and the designed frequency-splitting link ensure overall PTE of ...

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... compensation technique is also insensitive to mismatches and a high PCE of 94.1% is achieved. Thus, the stability and feasibility of delay compensation are guaranteed. Meanwhile, the high PCE active rectifier and the designed frequency-splitting link ensure overall PTE of the SWPDT system is up to 76.5% while delivering 40mW power to the load. Fig. 13 shows the transient waveforms of the FSK-ASK conversion. The V AC is the FSK carrier signal, which contains 9MHz and 10MHz frequency information. The 9MHz frequency corresponds to Manchester code "0" and the 10MHz carrier frequency corresponds to Manchester code "1". Thanks to the designed frequency-splitting link, the link has almost ...

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... modulated carrier is shown as the half waveform as it is also fed to the active rectifier. ILROs finish the FSK to ASK conversion as shown in Fig 13. The 9MHz signal (corresponding to code element "0") and the 10MHz signal (for code element "1"), both of which lie in the locking range of ILROs, differ in their output amplitude, which exhibits ASK modulation characteristics. ...

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... (1.0V), with an ASK MD of 4.7%. The output of the SL shows that both the ASK carrier signal and the envelope signal lie within their linear range, achieving different gain amplification for the ASK carrier signal and the envelope signal. MD of the ASK signal is increased to 10.9% by the P-type SL, which is a fit and robust modulation depth. Fig. 14 shows the demodulation results for the ASK signal, from top to bottom are the Manchester code stream from TX coil, the envelope output V ENV , the average output V AVG of V ENV , and the hysteresis comparator output V CMP . The data stream of 1.11Mbps is encoded to form a 2.22Mbps Manchester code stream and the simulation results show ...

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... from TX coil, the envelope output V ENV , the average output V AVG of V ENV , and the hysteresis comparator output V CMP . The data stream of 1.11Mbps is encoded to form a 2.22Mbps Manchester code stream and the simulation results show that the envelope output has a large conversion gain and the circuit can demodulate the code stream correctly. Fig. 15 shows the data and clock waveforms recovered by the Manchester decoder. At the top is a random bit stream with a DR of 1.11Mbps, in the middle is the recovered data, and at the bottom is the recovered clock signal. As can be seen from the results, the data and clock are recovered synchronously, with a clock period of 900ns, ...

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... is a random bit stream with a DR of 1.11Mbps, in the middle is the recovered data, and at the bottom is the recovered clock signal. As can be seen from the results, the data and clock are recovered synchronously, with a clock period of 900ns, corresponding to a frequency of 1.11MHz. The demodulation of 1.11Mbps random data is completed correctly. Fig. 16 shows the power consumption breakdown of the entire data demodulation circuit, consuming a total of 69.1µW on average, with an energy efficiency of 62.2pJ/b for data ...