(a) nMOS and (b) pMOS curves of normalized drain current i versus g m / I D . 

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Context 1

... from (1) and (2), the g m I D ratio is for nMOS and pMOS transistors. As expected, the observed spread of the values, when W is swept, is very tight. Hence, as ∂ f 1 /∂ V G ∂ ( log f 1 ) ∂ log I D / ( W / L ) said in the Introduction, for the final LUT, it is enough to ex- g m / I D = f 1 = ∂ V G = ∂ V G tract this curve for one medium-value MOST width. Here, the same applies for V DS . Because of the minor variations in these = f 2 I D / ( W / L ) = f 2 ( i ) . (3) dependences with W and V DS , the presented model is really Because ideally i = f 1 ( V G , V D , V S ) does not depend on the tran- useful for an analog designer. sistor width W for MOS transistors with equal length, the g m / I D ratio is determined by i . In real world, i is slightly dependent 2.1. f T versus g m / I D of W , for L fixed, -because of the I D dependence expressed in The intrinsic MOST transition frequency f T gives the analog (1)-, thus, for di ff erent MOST W , small variations of g m / I D ver- designer an idea of the frequency limits of nMOS and pMOS sus i are observed. From the above discussion, the curve g m / I D transistors. So, it is interesting to see the f T response of the versus i is considered an inherent characteristic of each CMOS 65-nm nMOS and pMOS transistors for di ff erent inversion lev- technology. This relation is strongly related to the performance els. To do so, lets study the definition of the transition frequency of analog circuits, it gives an indication of the transistor region g m of operation and provides a tool for calculating transistor di- f T = 2 π ( C gs + C gd + C gb ) (4) mensions, as presented in [8, 9]. Since in our proposed model all MOST characteristics are written as function of g m / I D , the where C gs , C gd and C gb are the intrinsic gate-source, gate-drain relation of (3) is flipped, and from now on the relation will be and gate-bulk capacitances of the MOST. For a fixed L o , as g m i = f 3 ( g m / I D ). and the intrinsic capacitances are both proportional to W , it is For the 65-nm CMOS technology studied here, previous as- expected that f T is quasi-independent of W . With the extracted sumptions are now verified. Figure 4 presents i versus g m / I D MOST data, it is observed that this hypothesis is reasonably for more than forty MOST widths between 0.6 μ m and 192 μ m, valid for the 65-nm technology here used, as shown in Fig. 5, L = L o = 60 nm and for four V DS = { 0 . 1 , 0 . 5 , 0 . 8 , 1 . 1 } V, either for the previously stated set of W and V DS . 4 This figure shows that nMOS transistors biased in strong in- micrometer MOSTs due to the shortening of the channel length, version achieve transition frequencies up to 200 GHz whereas as it is, in a first approximation, inversely proportional to the pMOS transistors reach 100 GHz. In deep weak inversion those transistor length L [2]. Its increment should be considered be- frequencies are reduced to levels below the gigahertz. Consid- cause it would strongly distort the behavior of RF circuits. For ering the very restrictive quasistatic limit in the working fre- example, in an LC tank-VCO, the MOST conductance g ds af- quency f 0 of one tenth of f T [2], for an nMOS transistor with fects the value of the final MOST transconductance chosen, and a g m / I D equal to 5 V − 1 , f 0 can be up to 20 GHz, whereas for a hence the bias current and the phase noise [16]; in an LNA a g m / I D of 25 V − 1 f 0 should be around the 100 MHz. This simple high g ds value drastically reduces the maximum gain achieved check lets the designer know the limitations of the technology by the amplifier [20]. and of the used model in terms of frequency for each inversion For the 65-nm technology and L = L o , the g ds / I D ratio is level. extracted as function of g m / I D for nMOS and pMOS transistors, as displayed in Fig. 7. Behavior of these curves is prac- 2.2. Bias Gate-Source Voltage ( V GS ) versus g m / I D tically linear in all g m / I D range when V DS is relatively high From (1) and (2) it is derived that V GS is function of g m / I D , ( V DS ≥ 0 . 5 V ) and the values are comparatively small, moving as depicted in Fig. 6. It means that the designer has a way of from around 0 . 5 V − 1 to 2 V − 1 , for all the range of W . Neverthe- directly estimate the value of V GS when the g m / I D ratio is fixed. less a shift in the curves is observed when V DS becomes small. A rapid growth is seen as we move simultaneously to low values of V DS and to states of strong inversion. Linear behavior 3. Other conductances and transconductances disappears because MOST enters in ohmic region. In fact, this information can be used to estimate the practical border from 3.1. Output conductance (g ds ) to I D ratio ( g ds / I D ) the MOST is clearly saturated. For example, for an NMOS Another fundamental small-signal parameter required to de- with a fixed V DS ≈ 0 . 2 V , the g ds / I D linear behavior correspond scribe the MOST behavior is the output conductance g ds . It to an inversion range of g m / I D > 10 V − 1 ; then, and according dramatically increases in nanometer transistors with respect to to the Fig. 6 the bias V GS to ensure the saturation of NMOS 5 should be V GS 0 5 V . However, when the same transistor V AW and V AS the Early voltage for weak and strong inversion has a V DS > 0 . 5 V , bias range for saturated operation has to be regions, respectively [2]. g m / I D > 3 and V GS < 0 . 8 V . To correctly use the LUTs of g ds / I D , the designer should have The observed increase of g ds / I D ratio at a fixed V DS when a rough idea of the range of values of V DS of each of the MOST moving towards weak inversion, happens because g ds / I D in the circuit. It is enough to know if the MOST would work in 1 / V A , where V A is the Early voltage in first-order channel length the ohmic or in the saturated region. For the latter, it is enough modulation formula, and, as Tsividis stands, V AW < V AS , with to considered the LUT associated to the medium value V DS of 6 the saturated range, i.e. V DS 0 5 V . As seen in Fig. 7, the This approach is valid if c xx has a minor spread when W and maximum error made in g ds / I D would be below 25%, which is V DS vary. an acceptable value for this MOST characteristic. Figure 9 presents the plots of the resulting five normalized capacitances of nMOS and pMOS transistor for the whole range 3.2. Bulk transconductance ( g mb ) to I D ratio ( g mb / I D ) of g m / I D , varying either V DS and W . The curves have the ex- If bulk and source terminals are not short-circuited, the pected form respect to the inversion region. The spread with transconductance g mb should be considered, despite its value V DS and W is, in all cases, below 10%, hence for 65-nm MOST, is generally smaller than g m ; otherwise, its e ff ect is discarded. the idea of using normalized capacitances in a design flow is a In this work it is studied the ratio g mb / I D against g m / I D . As very good option [20]. g mb is also proportional to the aspect ratio of the transistor [2], when it is divided by I D , the g mb / I D should be a weak func- 5. Noise parameters tion of W . This fact is clearly appreciated in Fig. 8, with V S B = { 0 . 0 , 0 . 3 , 0 . 6 } V. Also, little variation of g mb / I D with V S B When modeling white and flicker noise (the MOST most is observed. noticeable noise sources), semi-analytical models are utilized, as the equations that model these e ff ects are both very simple and wide known [2]. The noise current power spectral density 4. MOST normalized intrinsic capacitances (psd) of these two phenomenons together with the induced gate Considering again that the working frequencies of the RF cir- noise, referred at the drain of the MOS as i 2 d ( f ), are sketched cuit into design are below one tenth of f T , it is enough to con- in Fig. 10. In it, three regions are recognized: the flicker noise sider in an RF design the well-known five intrinsic capacitances zone, the white noise zone and the induced-gate noise zone. C xx where xx = { gs , gd , gb , bs , bd } , disregarding the other capac- The frequency of the asymptotic limit between the flicker noise itances and transcapacitances as well as non-quasistatic e ff ects. and the white noise zones, called corner frequency f c is also These capacitances change with the inversion level, as Tsividis shown. In this work, the induced gate noise is not studied, states [2]; and obviously they change with the transistor size. but a similar approach to the one followed with the other noise The intrinsic capacitances C xx can be expressed as sources can be pursued to find it. C xx = C ox f Cxx ( i ; W , L ) L = = L o WL o C ox f Cxx ( i ; W , L o ) pressed The white as [7] noise psd i 2 w , d is, for all inversion regions, ...

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... is observed that for moderate and weak inversion its value is constrained between 1.0 and 1.5; however for strong inversion The steps followed to design the CS-LNA, as studied in this parameter could reach values up to 3.5. For K F , in strong [20], are revisited here to specifically highlight the usage of inversion the spread with W and V DS is relatively high, whereas the proposed MOST model. The LNA design synthesis uses in weak inversion this parameter is almost independent of sizing the impedance matching approach either at the input and output and V DS . So if a high level of accuracy is required in the flicker of the LNA load, for the working f 0 ; MOST are considered as model, a set of W and V DS should be considered; otherwise a identical, having both the same g m / I D and I D . mean value of K F versus g m / I D can be used. In addition, the So, lets suppose that we choose a specific pair ( g m / I D , I D ). use of the exponent η reduces the error of K f to less than 0.5%, The following data can easily be derived from the MOST: at least for frequencies up to 10 MHz. The corner frequency of a MOST f c is obtained by making from data of Fig. 4, given g m I D , the value of i is deter- equal the psd expressions of white noise and flicker noise, (7) mined. With this value and I D , the MOST W is obtained. and (8), resulting in Also g is derived in this ...