FIGURE 3 - uploaded by Vinod Joshi
Content may be subject to copyright.
(a) Von-Neumann architecture showing logic and memory units. Both logic and memory are kept separate having their total area as X + Y and interconnects facilitate the communication between them. (b) LIM structure with stack integration having total area as either X or Y.
Source publication
![FIGURE 4. Block diagram of LIM structure [1], consists of sense...](profile/Vinod-Joshi-7/publication/338379423/figure/fig2/AS:847827940937728@1579149341774/Block-diagram-of-LIM-structure-1-consists-of-sense-amplifier-MOS-logic-structure-and_Q320.jpg)
One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed,...
Contexts in source publication
Context 1
... traditional Von-Neumann architecture, logic and memory block are located separately and communication between them is facilitated by wires and interconnects, as shown in the Figure 3(a). This strategy hampers the overall performance of chip. ...
Context 2
... is emerging trend [1], [77] which can offer solution to the increased leakage currents due to scaling and large interconnect delay observed in traditional architecture. In LIM structure non-volatile devices are distributed over logic circuit plane and placed close to each other (Figure 3 (b)). This tight integration reduces the overall area occupied and also shortens the interconnect distance. ...
Similar publications
Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32...
Citations
... With the help of innovative hybrid SHE-STT-MTJ-CMOS circuits, we suggested a LIM-based ALU. Using simulation, the proposed designs are compared to the results of the clocked CMOS ALU and the magnetic ALU, both of which are based on Double Pass Tansistor logic [12], [13] respectively. The Cadence tool with a 45nm CMOS library and a Magnetic Tunnel Junction model [11] is used for all hybrid SHE-STT-MTJ-CMOS circuit analysis. ...
... This component conducts both mathematical and logical computations. Block diagram of 1-bit ALU has shown in Figure 4 [13]. For arithmetic unit, Full adder circuit is designed. ...
... As a result, this would have an impact on the hybrid circuits' overall performance. Table IV compares the the DPT L − C 2 MOS − ALU [12], P-MALU [13] and the proposed ALU in terms of how much power they use, how many devices they have, and how long it takes for them to do their work.The proposed ALU adder uses 39 % less dynamic power than the DPT L − C 2 MOS − ALU adder and 12.5% less dynamic power than the P-MALU adder design. The ALU adder's overall power consumption is 28% lower than that of the DPT L−C 2 MOS − ALU adder and 16% lower than that of the P-MALU full adder. ...
... architectures like LIM, and In-Memory Computing (IMC) (Fig.1) serve as a successful alternative to charge-based electronics [4]. Consequently, several hybrid CMOS/MTJ logic designs ranging from magnetic flip-flops [5], non-volatile basic gates [6], and magnetic decoders [7] to magnetic full adders [8]- [12] and non-volatile magnetic arithmetic logical units [13], [14] have been reported in the literature. ...
... However, to the best of our knowledge not many hybrid CMOS/MTJ full adder designs using majority logic, following the LIM architecture, are reported in literature. Furthermore, the existing full adders [8]- [12] based on LIM are either partially non-volatile, where only few of the input operands are made non-volatile or they suffer from high power and area consumptions. Therefore, encouraged by the foregoing discussions, a Fully Non-Volatile Reconfig-urable Magnetic Full Adder (NVRMFA) (Figs.3,4,5) based on majority logic using hybrid CMOS/MTJ structure LIM architecture is presented in this article as the building block of a Fully Non-Volatile Reconfigurable Magnetic Arithmetic Logic Unit (NVRMALU). ...
... Full non-volatility is incorporated in our designs by employing a modified multi-context hybrid CMOS/MTJ LIM architecture (Fig.1) [22], where all the input operands are stored in the MTJs. Such a setup eliminates the need for backing up data during power loss scenarios as in the case of partially non-volatile counterparts [8]- [11]. Also, it is our understanding that the digital comparator functionality, a crucial operation, part of the processor datapath, is not included in the existing magnetic ALU designs reported in literature [13], [14]. ...
Spintronics has been garnering great success in resolving the shortcomings of conventional charge-based electronics and von-Neumann architecture by offering novel computational paradigms almost devoid of leakage effects and volatility issues of traditional CMOS systems. Especially, hybrid CMOS/MTJ circuits integrating all benefits of spintronics with well-evolved CMOS technology have been extensively investigated as candidates for building next-generation processors. Motivated by the importance of magnetic processors, in this work, a novel fully non-volatile reconfigurable magnetic arithmetic logic unit (NVRMALU) based on majority logic has been proposed. This paper encompasses the prospects of NVRMALU at both the architecture level and circuit level by discussing multi-context hybrid CMOS/MTJ LIM architecture and operation of the circuit. Furthermore, the simulation results of the proposed fully non-volatile reconfigurable magnetic full adder (NVRMFA) making up NVRMALU reveal a remarkable total power reduction by around six to forty-seven folds compared to its contemporary magnetic full adders (MFAs) discussed here. Also, NVRMALU is superior to double pass transistor clocked CMOS (DPTLCMOS) ALU in terms of power reduction by six times, thus qualifying it as an excellent normally OFF, Instant ON digital system. A four-bit extension of NVRMALU has been presented as a sign of the feasibility of the design for multi-bit applications. The transient analysis demonstrates nonvolatile and dynamic reconfigurable traits of NVRMALU in addition to functionality verification. Additionally, variability analysis has been performed to study the factors controlling read and write performances of hybrid circuits from a device-level perspective.
... e.g. [8][9][10][11][12][13][14][15]. In fact, MTJs with a superparamagnetic magnetic layer have already been explored for probabilistic computing [16][17][18][19][20][21]. ...
True random number generators are of great interest in many computing applications such as cryptography, neuromorphic systems and Monte Carlo simulations. Here we investigate perpendicular magnetic tunnel junction nanopillars (pMTJs) activated by short duration (ns) pulses in the ballistic limit for such applications. In this limit, a pulse can transform the Boltzmann distribution of initial free layer magnetization states into randomly magnetized down or up states, i.e. a bit that is 0 or 1, easily determined by measurement of the junction's tunnel resistance. It is demonstrated that bitstreams with millions of events: 1) are very well described by the binomial distribution; 2) can be used to create a uniform distribution of 8-bit random numbers; 3) pass multiple statistical tests for true randomness, including all the National Institute of Standards tests for random number generators with only one XOR operation; and 4) can have no drift in the bit probability with time. The results presented here show that pMTJs operated in the ballistic regime can generate true random numbers at GHz bitrates, while being more robust to environmental changes, such as their operating temperature, compared to other stochastic nanomagnetic devices. The results presented here show that pMTJs operated in the ballistic regime can generate true random numbers at GHz bitrates, while being more robust to environmental changes, such as their operating temperature, compared to other stochastic nanomagnetic devices.
... Although the carry look-ahead adder is quick, the layout and fan-out on some of the signals tend to get bigger as the number of bits increases, slowing down the addition. [7] The rise in power dissipation when the technology node descends into the deep submicron zone is one of the main issues for CMOS technology. [11]One of the most promising spintronic devices is magnetic tunnel junction (MTJ), which uses a spin transfer torque (STT) switching mechanism, because to its nonvolatility, speed, longevity, CMOS compatibility, and most signi cantly the issues caused by current CMOS technology may be resolved by minimal power dissipation discussed in the proposed technology. ...
Digital Computer Arithmetic is an aspect of logic design with the objective of developing algorithms in order to achieve effective utilisation of available hardware and resources. The Arithmetic and Logical Unit is the critical component of a microprocessor and a central processing Unit. ALU comprises of combinational and Arithmetic units that perform operations like AND, OR, NOR etc. and Addition, subtraction, multiplication respectively. Hence an algorithm with ultimate speed and minimum chip area are the most often used measures to determine the Efficiency of an algorithm. This Paper presents a fast scheme for arithmetic computations with reduced Area in order to achieve High Speed. Since there is a strong link between Algorithm and the technology used for its Implementation, Vedic sutras implementation in an FPGA environment due to its ease of Application is discussed here .This Paper addresses the design of High speed Architecture for Addition, Subtraction, Multiplication, Division operations using Vedic maths. The proposed Vedic Maths Sutras (computation protocol) that are discussed in the present work exhibits its efficiency in terms of speed and area utilisation, as validated on FPGA.
... It has an extra degree of freedom for computation. The spintronics research community has attracted much of the attention because already many efforts were made for various spintronics-based applications such as the development of nonvolatile (NV) memory [3][4][5][6][7][8], NV-logic implementation [9][10][11][12][13][14][15][16][17][18], and magnetic sensors for sensing magnetic field in pico-tesla range to the new growing technologies like neuromorphic computing and the brain-inspired computing, etc. [19][20][21]. In conventional electronics, which relies on the charge-based scalar quantity, the power (or heat) dissipation can be reduced up to a certain extent. ...
We have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.
... 4 illustrates the output waveform of Modified Booth Encoder. Here the 4-bit multiplier and multiplicand are given as inputs and 8-bit final product is the generated output. ...
This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its advantage through the minimization of the 1/2CVdd2 energy dissipation occurring every cycle. Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. Finally, A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and comparisons have been made. The analysis is carried out using the industry standard EDA design environment using 250 nm
technology libraries from Tanner. The results prove that the CEPAL 4-bit ALU is 55% more powerefficient than the CMOS 4-bit ALU at 100MHz and at 2.5V operating voltage
... From the table, it can be concluded that spintronic based MRAM is the best among the rest of the several nonvolatile embedded memory technologies. From the processing perspective, spintronic devices are being extensively explored in an entirely new class of computer architecture such as all spin logic (ASL) [37] and logic-in-memory (LIM) (or processing-in-memory (PIM)) [38][39][40][41][42]. LIM structures are hybrid in nature, i.e., it employs the contemporary spintronic as well as the current CMOS devices. ...
The field of spintronics has attracted tremendous attention recently owing to its ability to offer a solution for the present-day problem of increased power dissipation in electronic circuits while scaling down the technology. Spintronic-based structures utilize electron’s spin degree of freedom, which makes it unique with zero standby leakage, low power consumption, infinite endurance, a good read and write performance, nonvolatile nature, and easy 3D integration capability with the present-day electronic circuits based on CMOS technology. All these advantages have catapulted the aggressive research activities to employ spintronic devices in memory units and also revamped the concept of processing-in-memory architecture for the future. This review article explores the essential milestones in the evolutionary field of spintronics. It includes various physical phenomena such as the giant magnetoresistance effect, tunnel magnetoresistance effect, spin-transfer torque, spin Hall effect, voltage-controlled magnetic anisotropy effect, and current-induced domain wall/skyrmions motion. Further, various spintronic devices such as spin valves, magnetic tunnel junctions, domain wall-based race track memory, all spin logic devices, and recently buzzing skyrmions and hybrid magnetic/silicon-based devices are discussed. A detailed description of various switching mechanisms to write the information in these spintronic devices is also reviewed. An overview of hybrid magnetic /silicon-based devices that have the capability to be used for processing-in-memory (logic-in-memory) architecture in the immediate future is described in the end. In this article, we have attempted to introduce a brief history, current status, and future prospectus of the spintronics field for a novice.
... With the high demand for high-density memory storage applications, alternative memory technology has been intensively investigated for replacing conventional charge-based flash memory which suffers from charge loss and program errors with device scaling down. To break the bottle-neck of device scaling, several emerging memory technology attracts considerable attention, such as phase-change memory (PCM) [1], ferroelectric random access memory (FeRAM) [2,3], magnetic resistive random access memory (MRAM) [4], and resistive random access memory (RRAM). Among them, the resistive random access memory (RRAM) device holds great potential as an emerging candidate because of its simple design, high-speed operation, excellent scalability, and low power consumption [5][6][7][8]. ...
The sneak path current (SPC) is the inevitable issue in crossbar memory array while implementing high-density storage configuration. The crosstalks are attracting much attention, and the read accuracy in the crossbar architecture is deteriorated by the SPC. In this work, the sneak path current problem is observed and investigated by the electrical experimental measurements in the crossbar array structure with the half-read scheme. The read margin of the selected cell is improved by the bilayer stacked structure, and the sneak path current is reduced ~20% in the bilayer structure. The voltage-read stress-induced read margin degradation has also been investigated, and less voltage stress degradation is showed in bilayer structure due to the intrinsic nonlinearity. The oxide-based bilayer stacked resistive random access memory (RRAM) is presented to offer immunity toward sneak path currents in high-density memory integrations when implementing the future high-density storage and in-memory computing applications.
... The magnetic tunnel junction (MTJ) is a promising memory cell due to its non-volatility and good compatibility with current CMOS technology. 1 Memory devices using MTJs, such as spintransfer torques-magneto resistive random access memory (STT-MRAM), have been proposed as a novel L4 cache 2 and embedded memory. 3 However, STT-MRAM is known to have reliability and read disturbance problems because the write and read current both flow through the tunneling barrier of the MTJ. ...
We demonstrate the effect of shape deformation in spin–orbit torque magnetoresistive random access memory (SOT-MRAM) based on micromagnetic simulation by generating 1000 randomly deformed samples using the exponentially decaying autocorrelation function. The conventional in-plane magnetic field-assisted SOT write scheme and the recently proposed spin-transfer torque-spin-orbit torque (STT-SOT) hybrid write scheme were simulated and compared with the effect of the Gilbert damping constant (α) considered in the presence and the absence of the Dzyaloshinskii–Moriya interaction (DMI). We found that shape deformation of the MTJ can result in write failure or degradation of the switching time. To compensate the device-to-device performance variation induced by the shape deformation, the condition of high α and the presence of the DMI is desired for the magnetic field-assisted write scheme. The STT-SOT shows slight improvement in the switching performance for larger α and the presence of DMI while it retains 100% switching probability even with small α regardless of the DMI.
... In LIM structure, p-MTJs not only stores the bits, but also participate in logic operations. There are several circuits developed using hybrid STT-MTJ/CMOS LIM structures such as adders [10,11], ALU [12,13], decoder [14], logic gates [15,16], random number generator [17], non-volatile ternary content-addressable memory (TCAM) [18], non-volatile TCAM with priority-decision [19] etc. All these hybrid circuits occupy relatively smaller area and dissipates less power than its CMOS counterparts. ...
... For both conventional write circuit and proposed write driver, I W is driven by Vdda = 1.3 V which is higher than rest of the circuitry operating at Vdd = 1.1 V. During the simulation, 4T writing transistors set Fig. 3. STT switching mechanism in p-MTJ: When IW flows from free to fixed layer RAP changes to RP , whereas when IW flows from fixed to free layer RP changes to RAP [13]. ...
... To study the synchronous behavior with the LIM structure, we have integrated our write driver with the full adder proposed in Ref. [13] which is shown in the Fig. 9a. The proposed write driver has P,Q and R points of contact with the hybrid full adder circuit. ...
A novel self write-terminated driver is proposed for the hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuits based on logic-in-memory (LIM) structure. Using continuous write monitoring mechanism, the novel circuitry completely eliminates the unnecessary flow of write current which abolishes the wastage of write energy in the proposed write driver. Hence, the total energy required for writing process is reduced noticeably by 63.32% in novel write driver compared to the conventional write circuit. Monte-Carlo simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ. Simulations are also carried out for the proposed write driver, by varying the transistor sizes and supply voltage to analyze its switching probability to obtain safe operating region. Further, the proposed write driver is integrated with hybrid full adder to demonstrate its feasibility in low-power VLSI circuits.
