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(a) Tree based clock; (b) clock grid; (c) clock grid with clock gating. Clock gating can be added to the tree as well, and may be implemented at multiple levels.
Source publication
A RHBD clock distribution network is described that reliably synchronizes the flow of signals through an integrated circuit in the presence of SETs. The clock spine design controls both redundant and non-redundant hardened circuits. The design uses techniques to reduce the jitter due to SETs, as well as error detection at every clock edge, since er...
Contexts in source publication
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... systematic and random, but the former can be mitigated through good design. The most common clock distribution strategy is a tree (see Fig. 1(a)). The clock paths are buffered, starting from the source H-tree configuration using delay matched paths. The buffer drive strengths and capacitance of each node is progressively decreased as the signal propagates to the lower levels of hierarchy in the tree. In the mesh configuration, shown in Fig. 1(b), the buffered clock tree signals ...
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... clock distribution strategy is a tree (see Fig. 1(a)). The clock paths are buffered, starting from the source H-tree configuration using delay matched paths. The buffer drive strengths and capacitance of each node is progressively decreased as the signal propagates to the lower levels of hierarchy in the tree. In the mesh configuration, shown in Fig. 1(b), the buffered clock tree signals are shunted to create a clock grid or mesh structure. This grid structure has the advantage that since the branch resistances are in parallel, the effective clock skew is minimized-differences from driver circuits, either as designed in or due to such effects as power supply noise are averaged out. ...
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... dissipation increasingly limits modern microchips. Since gating the clocks eliminates active power dissipation in the sequential and intervening combinational logic, it is the most effective low power technique. Gated clocks must follow the tree topology, since individual branches are gated independently, as evident in Fig. 1(c). Thus, even mesh networks generally end in a tree as ...
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... Assertions in Gated Clocks-all modern commercial designs save power by using clock gating, which is, in general, more effective at finer granularities. Basically, clocks to circuits that are unused in that clock cycle are gated off, which eliminates both sequential circuit (flip-flop and latch) as well as combinational logic power, as shown in Fig. 1(c). It is possible to "grid" clocks at all levels, which reduces skew, and more importantly in a radiation tolerant design, increases clock node capacitance and thus SET resilience. However, fine-grained clock gating results in relatively low drive, low capacitance clock nodes, which are more susceptible to SETs. Moreover, clock gating ...
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... ions. Fluences from 5×10 5 to 2×10 7 particles/cm 2 were used. Beam angles from 0° to 79° (0° being the normal incidence) were used. The beam was incident on the die front (metallization) side. The effective LET ranged from 1.4 to 219.8 MeV-cm 2 /mg. For high speed I/O, the daughter board and the FPGA were mounted one below the other as shown in Fig. ...
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... clock spine was tested using 13.5 MeV/u and 49.3 MeV/u proton beams at the 88-inch cyclotron at Lawrence Berkley National Laboratory. The FPGA test board was separated from the beam using 3-foot cables (see Fig. 10(b). The cables and inability to shield the PLL from the protons limited the clock frequency, primarily by requiring PLL bypass, to 100 ...
Citations
... The local clock nodes are estimated to make up 20% of the overall SER [11]. Researchers from the industry and the academic field have developed techniques of designing local radiation-hardened clock drivers [12], [13]. The global clock network is believed to contribute to less than 0.1% of the overall clock path SER [11]. ...
Two types of clock networks including clock mesh and a buffered clock tree in a daisy-chain style were utilized to synchronize 5 DFF chains and fabricated in a 28 nm bulk CMOS technology. Alpha and proton particles did not trigger any errors indicating the significant single event tolerance of these clock networks. Heavy ion results for the data input pattern of checkerboard (alternate 1 and 0) are presented showing few occurrences of burst errors induced by single event transients (SETs) in the buffered clock tree at relatively high LET values. The same phenomena were observed in laser tests. Clock mesh is therefore proven to be less sensitive to SETs, if pre-mesh drivers do not generate transients. Otherwise, clock mesh possesses lower tolerance, as demonstrated in previous work. Moreover, these burst errors occurred (1) simultaneously in a DFF chain and its subsequent chains, or (2) in a single chain with subsequent chains unaffected. The distinct mechanisms of these burst errors were found to be the electrical masking effect of the daisy-chain clock buffers.
This brief presents a new clock-related
Single-Event Effect
(SEE) mitigation method for
Field Programmable Gate Arrays
(FPGAs). SEEs are most likely to happen in harsh environments, such as space, and are decently mitigated with
Triple Modular Redundancy
(TMR). However, clock tree triplication has a high cost for FPGAs; it reduces the total amount of usable clocks and introduces uncontrolled skew variation. Therefore, we propose to instantiate a
Programmable Local Clock Filter
(PLCF) close to TMRed sequential elements to locally triplicate the clock and filter the SEEs coming from the clock tree. The PLCF mitigation method has demonstrated 100% resilience to SEEs, which target either the clock tree or the PLCF’s logic. Thus, PLCF represents the first programmable clock-related SEE mitigation method and proposes a promising alternative to the state-of-the-art technics applied to FPGAs’ fabric.
This work discussed the state-of-the-art technology behind the various methods of the Single event hardened circuits, challenges and the approaching solutions. Here focusing is on the detrimental effects of natural radiation. There is a substantial requirement of developed technologies to keep safe the contents of memory and also in developing radiation-resistant components. Here a brief description of each of these approaches has been given. But, in all types of circuits, the digital hardening approaches are getting success while still there are barriers in the path of analog hardening. Here, the key challenges, while designing analog systems for high-end applications in front of the designers have been outlined and also available possible solutions so-far are being discussed.
With technology scaling down, the clock distribution networks (CDNs) in integrated circuits (ICs) are increasingly vulnerable to the single event transient (SET). The SET on the CDN can even lead to failure of the whole circuit. Therefore, it is important to evaluate in terms of SET susceptibility of the CDN. In this paper, a novel SET susceptibility analysis and evaluation methodology for CDN in any circuit is proposed. This methodology allows a more precise analysis of SET propagation in the CDN and the CDN-SET-induced incorrect latching by electrical simulations of circuits working in real time. In our simulations, injection location of the SET traverses all clock nodes on the CDN, injection time of the SET is random, and pulse width of the SET is random in a certain range. This can reflect more realistically and accurately how an IC works in the aerospace. Using the proposed methodology, we analyzed and evaluated the SET susceptibility of the CDN in a case circuit. The simulation results include SET propagation along the clock paths, the CDN-SET-induced incorrect data latching in the sequential elements, relative sensitivity of the clock nodes and sequential elements, and contributions of radiation-induced clock race and radiation-induced clock jitter to soft error rate (SER) of the case circuit. These results can supply information for the design of IC with high reliability. Moreover, our methodology can be used to analyze the factors influencing the SET sensitivity of CDN, and evaluate the hardening technique for CDN.
A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart - only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm2\mg LETEFF. We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.
Technology scaling in deep-sub micron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.
