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A CMOS pseudo-differential-input differential-output amplifier operating in class AB and exhibiting high-current-drive capability is presented. The circuit operates from a minimum supply of V<sub>T</sub>+2V<sub>DS,SAT</sub>, provides fast settling response, and also characterized by a wide input differential range with high linearity that enables i...
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... HE complementary differential amplifier, whose simpli- fied schematic is illustrated in Fig. 1(a), is a building block widely used in both analog and digital applications, such as in the implementation of voltage comparators, voltage and current amplifiers, and low-voltage differential-signaling (LVDS) sys- tems [1]- [5]. It is realized through the direct connection of two complementary source-coupled pairs, each serving as the ...
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... improved solution, limited for use in digital applications, is that in [6] and is referred to as the self-biased differential amplifier. It was originally employed in a TTL-to-CMOS input buffer and, more recently, in a LVDS transmitter circuit [7]. Its schematic diagram is shown in Fig. ...
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... proposed circuit useful in both analog and digital applications. Fig. 2 shows the schematic diagram of the proposed solution, which exploits two complementary versions of a pseudo-dif- ferential pair working in class AB, recently discussed in [9]- [12]. Thanks to this configuration, the differential-output capability of the traditional circuit in Fig. 1(a) is preserved and the supply requirements remain the same. In addition, the bias current in each branch is accurately set by transistor dimensions. Indeed, since in quiescent conditions transis- tors M1a-b (M2a-b) have the same gate-source voltage of M3 (M5), we get and . These equations also show an ideal balancing between and , ...
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... circuits in Fig. 1(a) and (b) and the proposed one were designed using a 0.35-m CMOS technology and were preven- tively simulated with Spectre within the Cadence environment. Transistor dimensions and bias settings are shown in Table I. Similar quiescent currents were set in the source-coupled pairs in order to perform a first fair comparison in terms of ...
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... I) and experimentally character- ized. The die micrograph is depicted in Fig. 9; the area occupied is 3624 m . The measured dc transfer characteristic was su- perimposed in Fig. 3, where a good agreement with simulations is displayed. The maximum current-drive capability was 1 mA, which is 50 times the standby current in the output transistors. Figs. 10-12 illustrate the single-ended time response to a rail-to rail input step under three load conditions (parallel RC load): pF pF and pF, respectively. The 1% settling time was 540, 20, and 65 ns, respectively. The linearity of the proposed circuit was then evaluated by applying a 100-kHz input voltage. Table III shows the third-order ...
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Citations
... and its internal structure employs Arbel-Goldminz as is illustrated in Fig. 1(b). [9], [10] negative output terminal is grounded. The transconductance gain, gm, can be varied over a wide range of values by adjusting an external dc bias current, that can be considered as an additional input signal. ...
... a) OTA Symbol and Equivalent Circuit[12] (b) Schematic diagram of the Internal Structure of the OTA[10]. ...
Carbon NanoTube Field Effect Transistor (CNTFET) is the new alternative and promising nano-scaled device for the implementation of high performance, and low power circuits. In this paper, comparison of CNTFET devices with MOSFET devices in the application of operational transconductance amplifier (OTA) in the GM-C filter is analyzed. The effect of capacitance with channel length, number of tubes, and chirality at frequency 5MHz is studied. The MOSFET filter uses 16 pF capacitors with the OTAs, whereas in the CNTFET filter only 0.8 pF capacitance is needed to achieve the same frequency response while preserving the same levels of total harmonic distortion. The proposed design of GM-C filter using CNTFET makes a reduction up to 95% of the capacitance needed over the MOSFET one, and also a reduction up to 95% in the bias current needed. Both are major benefits in the chip size, IC fabrication, and power consumption aspects.
... If this condition is not satisfied, the amplifier can experience a positive feedback connection during its slewing period that leads to large overshoots and degrades the settling-time performance [60,64]. To prevent this situation, as usually done in sub-threshold OTAs, slew-rate enhancers [65][66][67][68] or class-AB topologies [26,[69][70][71] must be used for the stages after the first one. In fact, a slew-rate enhancer is adopted for the last stage of the OTA in Figure 2, where the large capacitive load can dominate the slew-rate limitation. ...
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... So, this circuit cannot be used in those applications where power utilization has to be restricted and large capacitive loads have to be driven. There is another problem in this circuit that occurs due to current unbalance between I B1 and I B2 due to unavoidable process mismatches, which results in the saturation of the outputs [6]. To solve this issue, an additional common mode control section must be included. ...
... The deficiency in the circuit is further improved by Grasso and Pennisi in [9]. A similar solution is also presented by Giustolisi, Grasso and Pennisi in [6]. The authors exploit two complementary versions of a pseudo-differential pair working in class AB mode. ...
... In a classical differential amplifier, a differential input signal must be applied for differential operation of the amplifier and differential output signal is not achievable for a single ended input as emphasized in [6]. A possible solution to this problem is discussed in [10] and utilized in our design. ...
In this paper a CMOS rail to rail class AB opamp suitable for integrated battery powered systems is presented. The integrated battery powered systems require rail-to-rail input/output swing, high slew rate and low power consumption. The circuit is implemented in a UMC 1P-9M standard 90-nm CMOS technology. This circuit provides rail-to-rail input/output operation for the capacitive load of 100pF with better functionality with 2V single supply.
... There are many attempts to increase the performance of displays such as [6][7][8][9][10]. In [6], the designed circuit works well in terms of charging and discharging speed of large capacitors, but it has low bandwidth. ...
... In [6], the designed circuit works well in terms of charging and discharging speed of large capacitors, but it has low bandwidth. In [7] and [8], the designed circuits have a good bandwidth, but they do not have the ability to charge large capacitors well. In [9] developed circuit works well in terms of charging and discharging speed for relatively large capacitors, but it has a relatively high power consumption. ...
... The simulation results for the slew rate and bandwidth are shown in Fig. 7 and Fig. 8, respectively. Fig. 7 The simulation results for the slew rate of the proposed circuit Table 1 summarizes the simulation results of the proposed buffer amplifier in HSPICE in comparison with other buffer amplifiers [6][7][8][9][10]. ...
In this paper, a novel high-bandwidth and low-power buffer amplifier is presented for the liquid crystal display applications. This buffer amplifier consists of a folded cascade differential amplifier in the input and a class-AB amplifier in the output, which are designed carefully. The proposed buffer amplifier utilizes a high-performance feedback circuit to increase the bandwidth. It also utilizes a comparator circuit to avoid wasting power. The designed circuit has been simulated in 180 nm technology using HSPICE 2008.3. The simulation results show that the bandwidth, power consumption and power supply of the designed circuit are 1.14 MHz, 1.64 mW and 1.8 V, respectively.
... So, this circuit cannot be used in those applications where power utilization has to be restricted and large capacitive loads have to be driven. There is another problem in this circuit that occurs due to current unbalance between I B1 and I B2 due to unavoidable process mismatches, which results in the saturation of the outputs [6]. To solve this issue, an additional common mode control section must be included. ...
... The deficiency in the circuit is further improved by Grasso and Pennisi in [9]. A similar solution is also presented by Giustolisi, Grasso and Pennisi in [6]. The authors exploit two complementary versions of a pseudo-differential pair working in class AB mode. ...
... In a classical differential amplifier, a differential input signal must be applied for differential operation of the amplifier and differential output signal is not achievable for a single ended input as emphasized in [6]. A possible solution to this problem is discussed in [10] and utilized in our design. ...
In this paper, a CMOS differential input, differential output amplifier is presented. This amplifier operates in class AB mode and exhibits high current drive capability. The circuit is designed and implemented in a UMC 1P-9M standard 90-nm CMOS technology. It provides fast settling response of 235 ns while powered with 2 V. The proposed amplifier operates on a wide input differential range with high linearity exhibiting a P-1 dB of 10 dB. The circuit exhibits a differential current-drive capability of 2.9 mA. The presented amplifier has high gain-bandwidth product of 94 MHz. This differential amplifier provides a CMRR of 89 dB.
... Class-B can be ruled out since the quiescent biasing current is not null. As mentioned, in class-AB amplifiers the peak current is much larger than the quiescent current, [1], [26]- [28]; actually, this is one of the main requisites in class-AB amplifiers [23]. Large signal simulations of the proposed amplifier show that the total output current varies less than 15% around the quiescent current (this variation is due to common-mode variations). ...
... So, in fact there is some variation of the output current for large input signals but . Regarding the self-biasing part of the issue, in [7] and again exampled in [26], self-biasing is accomplished by using a differential-mode signal (usually one of the outputs). In this case the switching currents (under large signal conditions) can be significantly greater than the quiescent biasing current [7], [26], which would correspond to a class-AB output. ...
... Regarding the self-biasing part of the issue, in [7] and again exampled in [26], self-biasing is accomplished by using a differential-mode signal (usually one of the outputs). In this case the switching currents (under large signal conditions) can be significantly greater than the quiescent biasing current [7], [26], which would correspond to a class-AB output. In [9] and as is the case of the proposed amplifier, self-biasing is achieved by using a common-mode signal, which suffers less variations (unless the amplifier has CM instability) than differential-mode output signals. ...
A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.
... Fully differential self-biased amplifiers have already been proposed, such as, a folded cascode CMOS opamp (with and without gain boosting) [3], a class AB amplifier [4], and an LVDS signal receiver [5]. The amplifier reported in [4] is a pseudodifferential amplifier that relies on a complex active common-mode feedback (CMFB) network which has a separate biasing circuit, thus, is not completely selfbiased. ...
... Fully differential self-biased amplifiers have already been proposed, such as, a folded cascode CMOS opamp (with and without gain boosting) [3], a class AB amplifier [4], and an LVDS signal receiver [5]. The amplifier reported in [4] is a pseudodifferential amplifier that relies on a complex active common-mode feedback (CMFB) network which has a separate biasing circuit, thus, is not completely selfbiased. The LVDS signal receiver from [5] uses a continuous time CMFB circuit with resistors, thus lowering the achievable gain. ...
A CMOS self-biased fully differential amplifier is presented. Due to the self-biasing structure of the amplifier and its associated
negative feedback, the amplifier is compensated to achieve low sensitivity to process, supply voltage and temperature (PVT)
variations. The output common-mode voltage of the amplifier is adjusted through the same biasing voltages provided by the
common-mode feedback (CMFB) circuit. The amplifier core is based on a simple structure that uses two CMOS inverters to amplify
the input differential signal. Despite its simple structure, the proposed amplifier is attractive to a wide range of applications,
specially those requiring low power and small silicon area. As two examples, a sample-and-hold circuit and a second order
multi-bit sigma-delta modulator either employing the proposed amplifier are presented. Besides these application examples,
a set of amplifier performance parameters is given.
Application-Specific ICs (ASIC) are manufactured in bulk for a long time. In this paper, an approach to High-Speed Application-Independent IC (HS-AIIC) design is discussed. A resolution-selective (RS) and resolution-adaptive (RA) 8-bit Flash ADC are designed for use in various high-speed applications. With the choice of resolution, one can work with the trade-off between speed, power consumption, and resolution for a particular application. The proposed resolution selection algorithm can be implemented for any set of resolutions for a flash ADC design. Further, an adaptive block is added to make the ADC design adaptive in nature so that we do not have to select a particular resolution manually. The proposed design entrusts on saving manufacturing cost and increases the functionality of ADC on a single chip. Proposed resolution adaptive 8-bit flash ADC design dissipates 512[Formula: see text]mW of power with an ENOB of 7.56 bits and SNDR of 46.27[Formula: see text]dB for 1[Formula: see text]GHz sampling clock pulse.
