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An intermittent frequency synthesizer for fast duty-cycled receivers is presented in this paper. Different from state-of-art techniques which try to eliminate the initial phase error that degrades the intermittent frequency detection, a new frequency detector is proposed to maintain an accurate frequency detection regardless of the initial phase er...
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... with the time registers used in [14] and [15], the proposed detector can directly convert the input clocks time difference into charges stored on two identical capacitors, and then detect the difference by discharging simultaneously the capacitors. Fig.3 presents the schematic of the proposed frequency detector and its timing diagram. ...
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... with the time registers used in [14] and [15], the proposed detector can directly convert the input clocks time difference into charges stored on two identical capacitors, and then detect the difference by discharging simultaneously the capacitors. Fig.3 presents the schematic of the proposed frequency detector and its timing diagram. As shown in Fig. 3(a), the frequency detector is composed of switches SW1~SW6, resistors R1~R4, identical capacitors C1 and C2, inverters, a 2-NOR gate, and a delay cell. The circuit is controlled by a clearing signal CLR, two input clocks CK and CK , and a synchronizing signal RPC. Combing with its timing diagram in Fig. 3(b), the operating principle is ...
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... and its timing diagram. As shown in Fig. 3(a), the frequency detector is composed of switches SW1~SW6, resistors R1~R4, identical capacitors C1 and C2, inverters, a 2-NOR gate, and a delay cell. The circuit is controlled by a clearing signal CLR, two input clocks CK and CK , and a synchronizing signal RPC. Combing with its timing diagram in Fig. 3(b), the operating principle is described below: prior to the presence of the positive pulses on CK and CK , the switches SW1 and SW2 are turned on by CLR to charge the capacitors C1 and C2, and reset their voltages í µí± and í µí± to the supply voltage í µí± , and hence turns the outputs DW and UP low. When, positive pulses on CK and ...
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... of the VCO and the HSD during their settling [12], EN2 should lag behind EN1 by a sufficient amount of time (about 300ns in this design). Following these two one-shot pulses on CK and CK , RPC turns high for an sufficient long period to give rise to the frequency detection results UP and DW along with the sampling clock CK as described in Fig. 3(b). According to UP and DW , UDC, controlled by CK , updates its output DN which is sent to the DAC through an SPI to adjust the VCO's tuning voltage í µí± . If UP is high and DW is low, í µí± increases, so does the VCO's oscillating frequency í µí± , while UP is low and DW is high, í µí± and í µí± decrease. UDC also outputs a signal ...
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... with the time registers used in [14] and [15], the proposed detector can directly convert the input clocks time difference into charges stored on two identical capacitors, and then detect the difference by discharging simultaneously the capacitors. Fig.3 presents the schematic of the proposed frequency detector and its timing diagram. ...
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... with the time registers used in [14] and [15], the proposed detector can directly convert the input clocks time difference into charges stored on two identical capacitors, and then detect the difference by discharging simultaneously the capacitors. Fig.3 presents the schematic of the proposed frequency detector and its timing diagram. As shown in Fig. 3(a), the frequency detector is composed of switches SW1~SW6, resistors R1~R4, identical capacitors C1 and C2, inverters, a 2-NOR gate, and a delay cell. The circuit is controlled by a clearing signal CLR, two input clocks CK and CK , and a synchronizing signal RPC. Combing with its timing diagram in Fig. 3(b), the operating principle is ...
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... and its timing diagram. As shown in Fig. 3(a), the frequency detector is composed of switches SW1~SW6, resistors R1~R4, identical capacitors C1 and C2, inverters, a 2-NOR gate, and a delay cell. The circuit is controlled by a clearing signal CLR, two input clocks CK and CK , and a synchronizing signal RPC. Combing with its timing diagram in Fig. 3(b), the operating principle is described below: prior to the presence of the positive pulses on CK and CK , the switches SW1 and SW2 are turned on by CLR to charge the capacitors C1 and C2, and reset their voltages í µí± and í µí± to the supply voltage í µí± , and hence turns the outputs DW and UP low. When, positive pulses on CK and ...
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... of the VCO and the HSD during their settling [12], EN2 should lag behind EN1 by a sufficient amount of time (about 300ns in this design). Following these two one-shot pulses on CK and CK , RPC turns high for an sufficient long period to give rise to the frequency detection results UP and DW along with the sampling clock CK as described in Fig. 3(b). According to UP and DW , UDC, controlled by CK , updates its output DN which is sent to the DAC through an SPI to adjust the VCO's tuning voltage í µí± . If UP is high and DW is low, í µí± increases, so does the VCO's oscillating frequency í µí± , while UP is low and DW is high, í µí± and í µí± decrease. UDC also outputs a signal ...
Citations
... When CK L turns high, the discharge continues and V C drops toward the threshold voltage V TL of the buffer. Once V C is lower than the threshold voltage, the output CK O becomes low and the time interval from the rising edge of CK L to the falling edge of CK O can be calculated by [10]: ...
... After the pulse on S P3 comes, a reference pulse with a duration of t REF is launched on S REF . According to (9), the pulse duration can be calculated by: (10) where D TH is the threshold duty cycle, T PWM is the pulse duration of S P2 equal to the corresponding period of CK PWM . Simultaneous with the production of the pulse on S REF , the signal S P2 is fed to the duty-cycle comparator for resetting, while the current pulse on CK PWM is captured on the signal S DC by the signal S P3 through a two-input AND gate. ...
A novel duty‐cycle‐sensing overload detector for DC‐DC converter is proposed in this paper. Firstly, the theoretical analysis is conducted to reveal the susceptibility of the conventional overload detectors to temperature variation and the input/output‐voltage change of the DC‐DC converter. Then, the schematic of the novel duty‐cycle‐sensing overload detector is presented and its operation principle is analyzed. Thanks to the time register, the proposed detector generates a theoretically voltage‐and‐temperature‐insensitive threshold duty cycle, compares it with the real‐time duty cycle of the converter's PWM signal, and announces an overload event if the real‐time duty cycle exceeds the threshold. Finally, a prototype of a BUCK DC‐DC converter including the proposed detector and a conventional current‐sensing overload detector is constructed and measured. As the measurement results show, the threshold duty cycle only varies by about 2.4% as the temperature changes from 0 to 90 °C while the threshold voltage of the conventional current‐sensing detector changes by about 4.6%. The proposed detector can keep effective even the temperature rises to 90 °C while the conventional current‐sensing detector can work at a temperature no higher than 85 °C. Without circuitry modification, the proposed detector correctly senses the overload event as the DC‐DC converter's output voltage changes in a range of 2.1–2.9 V while the conventional one loses its effectiveness if the output voltage is set higher than 2.54 V. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.
... AFSK modulation was used for sending control commands at a data rate of 1.2 kbps [86]. While GMSK was used for data uplink and downlink at a rate of 9.6 kbps [86], [87]. The system used the UHF band for data link and the VHF band for the control line. ...
Small satellite communications recently entered a period of massive interest driven by the uprising commercial and civil space applications and motivated by various technological advances. Miniaturized satellites, known as CubeSats, are particularly attractive due to their low development and deployment costs which makes them very promising in playing a central role in the global wireless communication sector with numerous applications ranging from Earth imaging and space exploration to military applications. Moreover, constellations of CubeSats in low Earth orbits (LEOs) can meet the increasing demands of global-coverage low-cost high-speed flexible connectivity. However, this requires innovative solutions to overcome the significant challenges facing high-data-rate low-power space communications. This paper provides a comprehensive review of the design, protocols, and architectures of state-of-the-art CubeSat communication subsystems with a particular focus on their baseband structures. The literature is surveyed in detail to identify all design, testing, and demonstration stages as well as accurately describe the systems’ architectures and communication protocols. The reliability, performance, data rate, and power consumption of the reviewed systems are critically compared and evaluated to understand the limitations of existing CubeSat transceivers and identify directions of future developments. It is concluded that CubeSat communication subsystems still face many challenges, namely the development of energy-efficient high-speed transceivers that satisfy CubeSats’ cost, mass, size, and power constraints. Nevertheless, several directions for improvements are proposed such as the use of improved channel coding algorithms, Field Programmable Gate Arrays (FPGAs), beamforming, advanced antennas, deployable solar panels, and transition to higher frequency bands. By providing a concrete summary of existing CubeSat on-board transceiver designs and critically evaluating their unique features and limitations as well as offering insights about potential improvements, the review should aid CubeSat developers, researchers, and companies to develop more efficient high data rate CubeSat transceivers.
... By the time register, time-domain signals can be operated, saved, and reproduced precisely. By this, we implemented a conventional type-II analog PLL [17] and a digital FLL [18] respectively. Based on our previous works, an analog intermittent FLL (IFLL) is proposed, analyzed, optimized, and implemented in this paper which can solve SRR's frequency calibration mentioned above. ...
... In other words, when frequency calibration ongoing, SRR runs at normal. Compared with our previous work in Ref. [18], the proposed analog loop can obtain an infinite frequency-error detecting accuracy and a fast settling behavior to fulfill the requirement of SRR's frequency synthesizer. Notably, according to our literature retrieval, this is the first design that can provide background frequency calibrations and resonant frequency adjustments for SRR with a fine frequency resolution and without interruption to SRR's receiving operation. ...
The conventional phase-locked loops or frequency-locked loops should take time to calibrate the oscillator’s resonant frequency in a super-regenerative receiver (SRR) and severely disrupts the receiver’s operations. This paper proposes a novel intermittent frequency locked loop (IFLL) as a frequency synthesizer to continuously maintain the resonant frequency equal to the preset target frequency without interruption to the SRR. An analog loop mainly composed of a time-register-based frequency detector and a charge pump is proposed to achieve precise frequency detection during each SRR’s quenching period regardless of the inevitable initial phase error, and adjust SRR’s resonant frequency accordingly. An average fractional division scheme is adopted to improve IFLL’s frequency resolution to the level of the quenching frequency. The operations of the IFLL are analyzed with the z-domain transfer function, including the stability and frequency response. A prototype is built and tested. The measurement results show that the proposed IFLL only needs a calibration cycle of fewer than 50 μs to adjust SRR’s resonant frequency without interruption against its receiving. The real-time frequency error after calibration is smaller than 70 kHz. SRR opposes a sensitivity of -61.2 dBm @ 200 kbps and a 3-dB bandwidth of 2.2 MHz.
