Figure 3 - uploaded by Kunwar Singh
Content may be subject to copyright.
Source publication
This chapter presents a comprehensive overview of the conventional fully static master slave flip-flops
used in low power VLSI systems where power budget is critical. In addition, the chapter also presents
alternative realization of fully static master-slave flip-flops utilizing a modified feedback strategy. The
flip-flops designed on the basis of...
Contexts in source publication
Context 1
... soon as the clock is OFF, the logic level at the output node is no longer reliable and may be lost due to subthreshold leakage at modern process nodes. To overcome this problem, regenerative looping action is provided by using inverters in the feedback paths as shown in Figure 3 to hold the logic levels correctly (Weste & Harris, 2011). Hence, the resulting circuit configurations become static in nature. ...
Context 2
... smaller number of transistors in the feedback path lead to lesser interconnections and as an immediate consequence the delays due to these interconnects are also reduced. Figure 13 depicts the variation of average power dissipation with C in for 16X loading condition. WPMS and PTLFF display worst power dissipation characteristics mainly because of short circuit power dis-sipation at internal nodes of the FF in the critical path due to threshold voltage drop. ...
Context 3
... leads to reduced internal power dis- sipation at these nodes as lesser capacitance has to be charged or discharged per clock cycle. However, reduction in the clock load of mC 2 MOSff1 due to transistors eliminated from the feedback structure is nullified due to PMOS transistors TP19 and TP20 whose size is twice that of transistors TP2 and TP6 in case of TGFF and as a result the total power dissipation of both the FFs is nearly the same as can be clearly observed from Figure 13. ...
Similar publications
This chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are impr...
This paper proposes an improvised D- flip flop configuration based on tristate inverter logic, which reduces the power dissipation, decrease the transition time from the input to output as well as reduced time to reach rail to rail voltage. The flip flop uses transmission gate instead of pass transistor to achieve this requirement. The design is si...
Abstract—The most important criteria for the design and
implementation of DSP processor is area optimization and
reduction in power consumption. The fundamental block for
the design and implementation of the DSP processor is the
Finite Impulse Response Filter. The Finite Impulse Response
(FIR) Filter consists of three basic modules which are adder...
Low Power and High performance JK Flip-Flop using 45 nm Technology [1] G. Naveen Balaji [2] V. Narayanan, [3] V.S. Nivash [1] Assistant Professor [2] [3] UG Student [1][2][3] Abstract:-In current scenario, VLSI circuit's greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to grea...
p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in...
Citations
This chapter presents new methods and software system SOSNA intended for the parameter optimization of heat supply systems. They make it possible to calculate large-scale systems which have a complex structure with any set of nodes, sections, and circuits. A new methodological approach to solving the problem of the parameter optimization of the heat supply systems is developed. The approach is based on the multi-level decomposition of the network model, which allows us to proceed from the initial problem to less complex sub-problems of a smaller dimension. New algorithms are developed to numerically solve the parameter optimization problems of heat supply systems: an effective algorithm based on the multi-loop optimization method, which allows us to consider hierarchical creation of the network model in the course of problem solving; a parallel high-speed algorithm based on the dynamic programming method. The new methods and algorithms were used in the software system SOSNA.
