Fig 2 - uploaded by Bulusu Anand
Content may be subject to copyright.
(a) Simulated structure of the SOI-NMOS device with a body contact made as in [1]. L = 0:1 m, W = 10 m and the thickness of the silicon film is 35 nm. (b) Structure used to explain the body effect qualitatively in a practical DTMOS device.
Source publication
We study the body effect in silicon-on-insulator (SDI) devices to determine if enhanced drive currents can be obtained with a body bias equal to the supply voltage. We find that significantly enhanced drive currents are observed only when the film thickness is sufficiently large. We explain this phenomenon using two-dimensional (2-D) device simulat...
Contexts in source publication
Context 1
... simulate DTMOS using the SOI device (FD) described earlier, we have created, as in [1], a body contact below the device [ Fig. 2(a)] and tied it to the gate terminal. The supply voltage ( ) was chosen as 0.6 V. In the case of the NMOS device with a film thickness of 35 nm, a 16% increase in drive current ( ) is observed in DTMOS operation over conventional MOS operation. We have then repeated the simulations for various silicon film thicknesses ranging from 35 nm ...
Context 2
... explain this observation as follows. Let the body potential (at the silicon-BOX layer interface) in the SOI device when the body is not connected to gate be and the floating body poten- tial [see Fig. 2(a)]. For a significant increase in current drive, the applied body bias should be much larger than because only then would the depletion charge under the gate decrease appre- ciably, increasing the inversion charge correspondingly. This is essentially the principle of operation of ...
Context 3
... practice, the body contact is not given from the bottom. To understand the behavior of a practical device, we simulated the device shown in Fig. 2(b). It is a long channel ( m) FDSOI device (silicon film thickness is 35 nm) without drain (n ) diffusion as shown. We shall now examine the necessary condition for a significant increase in drive current in DTMOS ...
Citations
... For the conventional MOSFET to operate in triode or saturation regions, it is necessary that the applied voltage between the gate and source terminals be higher than the threshold voltage. The DTMOS technique is applied to achieve improved performance by allowing the same regions of operation to be reached with lower gate voltage [11][12][13]. ...
For the first time, Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) n-channel with Dynamic Threshold MOS configuration (DTMOS) using the SELBOX (Selective Buried OXide) substrate will be analyzed. The drain and substrate current, transconductance (gm) and Subthreshold Slope (SS) will be compared in the DTMOS mode and the standard biasing configuration for different gap width (WGAP) of SELBOX. Additionally, the output conductance and the transconductance gain also studied through numerical simulations. The results indicate that the SELBOX structure in DTMOS mode is competitive candidates for analog applications.
... Moreover the total masks needed in the front-end process for FD SOI devices are less than half of that required for bulk CMOS devices [15]. Because of BOX layer the fully depleted silicon-on insulator (FD-SOI) has the advantages of lower parasitic junction capacitance and better sub-threshold swing, reduced short channel effects [16][17]. ...
A two–dimensional (2-D) numerical model for measurement of the surface potential variation along the channel length/width in fully depleted silicon-on-insulator MOSFET is developed by recursively using self consistent solutions of Poisson’s equation with Schrödinger equation. The model developed is used to investigate the short-channel effects (SCEs). The model is extended to find the threshold voltage, sub-threshold slope and DIBL in the deep submicron regime of MOSFETs. The model is used to successfully find appropriate metal work function for the desired threshold voltage of FD-SOI MOSFET. A GUI in Matlab is created to facilitate the user interface of the model and make it more user-friendly.
... Moreover the total masks needed in the front-end process for FD SOI devices are less than half of that required for bulk CMOS devices [15]. Because of BOX layer the fully depleted silicon-on insulator (FD-SOI) has the advantages of lower parasitic junction capacitance and better sub-threshold swing, reduced short channel effects [16][17]. ...
A two–dimensional (2-D) numerical model for measurement of the surface potential variation along the channel length/width in fully depleted silicon-on-insulator MOSFET is developed by recursively using self consistent solutions of Poisson’s equation with Schrödinger equation. The model developed is used to investigate the short-channel effects (SCEs). The model is extended to find the threshold voltage, sub-threshold slope and DIBL in the deep submicron regime of MOSFETs. The model is used to successfully find appropriate metal work function for the desired threshold voltage of FD-SOI MOSFET. A GUI in Matlab is created to facilitate the user interface of the model and make it more user-friendly.
... To overcome this, a Novel SOI-DTMOS structure has been proposed [3]. SOI technology is attractive for DTMOS operation due to the absence of substrate loading and substrate coupling problems that are encountered in Bulk DTMOS devices [1,4]. SOI MOS has become a competitive technology for RFIC implementations mainly due to low-cost, high performance mixedmode circuits, higher level of integrability, low-power, etc [5]. ...
... C jsswgo is the source (gate-side) sidewall junction capacitance at zero bias i.e. V BS = 0, given as (4) where, X j is junction depth which varies with T si in DTMOS and is constant in Novel structure. W d is depletion width. ...
... LS/D is the length of source and drain junctions and R´s heet can be written as (11) Analytical variation of RbCb delay with T si for SOI-DTMOS and Novel structure is shown in fig. 2. This is in conformity with [4]. increase in C b and thus the value of R b C b nearly saturates. ...
A 2.5 GHz Low Noise Amplifier (LNA) intended for use in low-voltage and low-power applications was designed and simulated using Silicon on Insulator-Dynamic Threshold Voltage MOSFET (SOI-DTMOS) transistor and SOI-DTMOS based Novel structure transistor in 0.25µm CMOS SOI technology for V DD = 0.8 V. A differential cascode topology using inductive source degeneration was used. Complying with the aspects of noise optimization, linear gain and impedance matching the design methodology of LNA was analyzed in detail. Comparison of SOI-DTMOS LNA and SOI-DTMOS based Novel structure LNA shows that noise figure and gain of Novel structure based LNA is much better. The DTMOS LNA circuit shows even better performance than 0.25µm CMOS SOI LNA designed for V DD = 2 V. Keywords DTMOS, Delay in CMOS, LNA, Silicon film thickness, Silicon-on-Insulator (SOI) I. Introduction Developing wireless communication is one of the most important factors for the next-generation information technology. The increasing demand on portable devices has motivated the development of low-power radio frequency integrated circuits (RFICs) in Metal Oxide Field Effect Transistor (MOSFET) Technology [1]. The most common approach used for low power applications is supply voltage scaling, but this causes the reduction of gate overdrive in MOSFET, and hence degradation of the circuit speed. Therefore scaling of the power supply should be accompanied by threshold voltage reduction [2]. However, the lower limit for scaling threshold voltage is set by the amount of off-state leakage current that can be tolerated. Device engineering can be effectively used to extend the lower bound of supply voltage to ultra-low voltage applications. Dynamic Threshold Voltage MOSFET (DTMOS) is one such device having a high threshold voltage VTH at zero bias resulting in small leakage current; and a low threshold voltage at V GS = V DD resulting in a higher current drive than standard MOSFET for lower supply voltages [2]. However, the large body capacitance and the delay in charging the body are serious challenges in implementing the SOI-DTMOS. To overcome this, a Novel SOI-DTMOS structure has been proposed [3]. SOI technology is attractive for DTMOS operation due to the absence of substrate loading and substrate coupling problems that are encountered in Bulk DTMOS devices [1, 4]. SOI MOS has become a competitive technology for RFIC implementations mainly due to low-cost, high performance mixed-mode circuits, higher level of integrability, low-power, etc [5].
... To overcome this, a Novel SOI-DTMOS structure has been proposed [3]. SOI technology is attractive for DTMOS operation due to the absence of substrate loading and substrate coupling problems that are encountered in Bulk DTMOS devices [1,4]. SOI MOS has become a competitive technology for RFIC implementations mainly due to low-cost, high performance mixedmode circuits, higher level of integrability, low-power, etc [5]. ...
... C jsswgo is the source (gate-side) sidewall junction capacitance at zero bias i.e. V BS = 0, given as (4) where, X j is junction depth which varies with T si in DTMOS and is constant in Novel structure. W d is depletion width. ...
... LS/D is the length of source and drain junctions and R´s heet can be written as (11) Analytical variation of RbCb delay with T si for SOI-DTMOS and Novel structure is shown in fig. 2. This is in conformity with [4]. increase in C b and thus the value of R b C b nearly saturates. ...
A 2.5 GHz Low Noise Amplifier (LNA) intended for use in low-voltage and low-power applications was designed and simulated using Silicon on Insulator-Dynamic Threshold Voltage MOSFET (SOI-DTMOS) transistor and SOI-DTMOS based Novel structure transistor in 0.25µm CMOS SOI technology for V DD = 0.8 V. A differential cascode topology using inductive source degeneration was used. Complying with the aspects of noise optimization, linear gain and impedance matching the design methodology of LNA was analyzed in detail. Comparison of SOI-DTMOS LNA and SOI-DTMOS based Novel structure LNA shows that noise figure and gain of Novel structure based LNA is much better. The DTMOS LNA circuit shows even better performance than 0.25µm CMOS SOI LNA designed for V DD = 2 V. Keywords DTMOS, Delay in CMOS, LNA, Silicon film thickness, Silicon-on-Insulator (SOI) I. Introduction Developing wireless communication is one of the most important factors for the next-generation information technology. The increasing demand on portable devices has motivated the development of low-power radio frequency integrated circuits (RFICs) in Metal Oxide Field Effect Transistor (MOSFET) Technology [1]. The most common approach used for low power applications is supply voltage scaling, but this causes the reduction of gate overdrive in MOSFET, and hence degradation of the circuit speed. Therefore scaling of the power supply should be accompanied by threshold voltage reduction [2]. However, the lower limit for scaling threshold voltage is set by the amount of off-state leakage current that can be tolerated. Device engineering can be effectively used to extend the lower bound of supply voltage to ultra-low voltage applications. Dynamic Threshold Voltage MOSFET (DTMOS) is one such device having a high threshold voltage VTH at zero bias resulting in small leakage current; and a low threshold voltage at V GS = V DD resulting in a higher current drive than standard MOSFET for lower supply voltages [2]. However, the large body capacitance and the delay in charging the body are serious challenges in implementing the SOI-DTMOS. To overcome this, a Novel SOI-DTMOS structure has been proposed [3]. SOI technology is attractive for DTMOS operation due to the absence of substrate loading and substrate coupling problems that are encountered in Bulk DTMOS devices [1, 4]. SOI MOS has become a competitive technology for RFIC implementations mainly due to low-cost, high performance mixed-mode circuits, higher level of integrability, low-power, etc [5].
... However, the lower limit of the threshold voltage is set by the amount of off-state leakage current that can be tolerated, ideally should be no less than 0.4V [6]. Because of BOX layer the fully depleted silicon-oninsulator (FDSOI) has the advantages of lower parasitic junction capacitance and better subthreshold swing, reduced short channel effects, and free of kink effect [2,8,9]. Especially with the geometry scaling down to deep sub-micron range, the threshold voltage also scale down, therefore, threshold voltage control is becoming more important for the future technology. ...
... (9) transconductance measured by the slope of I ds -V gs curve. When Id-Vg curve of a device is steeper it shows better transconductance. ...
FULLY DEPLETED (FD) SILICON ON INSULATOR (SOI) METAL OXIDE FIELD EFFECT TRANSISTOR (MOSFET) ISTHE LEADING CONTENDER FOR SUB 65NM REGIME. THIS PAPER PRESENTS A STUDY OF EFFECTS OF WORKFUNCTIONS OF METAL GATE ON THE PERFORMANCE OF FD-SOI MOSFET. SENTAURUS TCAD SIMULATIONTOOL IS USED TO INVESTIGATE THE EFFECT OF WORK FUNCTION OF GATES ON THE PERFORMANCE FD-SOIMOSFET. SPECIFIC CHANNEL LENGTH OF THE DEVICE THAT HAD BEEN CONCENTRATED IS 25NM. FROMSIMULATION WE OBSERVED THAT BY CHANGING THE WORK FUNCTION OF THE METAL GATES OF FD-SOIMOSFET WE CAN CHANGE THE THRESHOLD VOLTAGE. HENCE BY USING THIS TECHNIQUE WE CAN SET THEAPPROPRIATE THRESHOLD VOLTAGE OF FD-SOI MOSFET AT SAME VOLTAGE AND WE CAN DECREASE THELEAKAGE CURRENT, GATE TUNNELLING CURRENT AND SHORT CHANNEL EFFECTS AND INCREASE DRIVECURRENT.
... A DTMOS was designed in the device simulator ATLAS [4]. The device had film thickness of 100 nm and behaves as a partially depleted (PD) SOI [5]. It has buried oxide thickness (BOX) thickness of 200 nm and gate oxide thickness (T ox ) of 3.9 nm. ...
A low voltage low-power class-E power amplifier circuit is designed using 0.25 µm DTMOS. This circuit exhibits very good performance at very low supply voltages (0.8 V). Its maximum efficiency over a range of input RF power levels is greater than 95% and power dissipated in the network is less than 1 mW. This circuit in comparison with a 0.25 µm SOI-CMOS circuit shows better performance at low input RF power levels. For comparison purpose a Class-E power amplifier was designed in 0.6 μm bulk CMOS using 4.5 V V DD and 1 V V GS. This power amplifier develops an output power of 0.328 W and has an efficiency of 80% at operating frequency of 1 GHz. A comparison was also made between the designs using 0.6 μm bulk CMOS and 0.6 μm SOI-CMOS as transistors operating in switch mode. The SOI-MOS based shows better performance. But the actual aim of this work being the designing of class-E low voltage low power amplifier, SOI-MOS based circuit did not satisfy our set design criteria.
... Dynamic threshold MOSFET (DTMOS) operation [3] offers a solution to this problem since a near ideal sub-threshold slope and larger are realizable with these body-tied-to-gate structures. Partially depleted silicon-on-insulator (PDSOI) technologies, with silicon film thickness larger than or equal to the depletion width in the silicon film are reported to be superior for DTMOS operation [4]. However, the large body capacitance [5] and the delay in charging the body [6] are serious issues in implementing SOI-DTMOS. ...
The performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We show that the body RC time constant reduces up to a certain value of silicon film thickness, and then saturates. However, delay of a DTMOS circuit is affected not only by the RC delay of the body but also by the additional load capacitance, which appears due to the gate to body contact. In this paper, we propose a model for PDSOI-DTMOS circuit delay, taking the effect of body parasitics into account, and use it to study the circuit delay as a function of silicon film thickness. Using this model, we show that the optimum value of silicon film thickness is approximately equal to the depletion width in the silicon film in a typical sub-100-nm PDSOI-DTMOS technology.
... [2,3] However, the lower limit of the threshold voltage is set by the amount of off-state leakage current that can be tolerated, ideally should be no less than 0.4V. [2] The fully depleted silicon-on-insulator (FDSOI) has the advantages of lower parasitic junction capacitance and better sub-threshold swing, reduced short channel effects, and free of kink effect [4], [5], [9]. Especially with the geometry scaling down to deep sub-micron range, the threshold voltage also scales down, therefore, threshold voltage control is becoming more important for the future technology. ...
In this paper, the threshold voltage of fully depleted silicon on insulator device with geometry scale down below 100 nm is investigated deeply. All the device simulations are performed using SILVACO Atlas device simulator. Several ways to control the threshold voltage are proposed and simulated. Threshold voltage changing with the silicon film thickness, channel doping concentration, gate oxide thickness and gate electrode work function is simulated. One short channel NMOS and one PMOS FDSOI device structure with effective channel length 90 nm and 30 nm silicon film thickness are designed.
Electrical characteristics performance comparison between partially-depleted SOI and n-MOS Devices in order to compare their electrical characteristics using Silvaco software is done and presented in this paper.One specific channel lengths of the Device that had been concentrated as 0.4 micron. The comparisons were focused on three main electrical characteristics that are leakage current, threshold voltage and subthreshold voltage. The device structures were constructed using Silvaco-Athena and the characteristics were examined and simulated using Silvaco-Atlas. Results were analysed and presented to show that the electrical characteristics of partially-depleted SOI devices are better than that of bulk-Si devices. It has also shown that the partially depleted SOI device is superior in the submicron region.
