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A low-density parity-check code (LDPC) is one of the classical error-correcting code for message transmission over noisy channel. It meets desired Shannon limit performance and is adopted as a data channel for the 5th generation new radio (5G NR) standard. This paper investigates the LDPC decoder by applying minimum-sum (MS) algorithm on the base m...
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Citations
... The work [35] use SCL with better error-correcting performance than all other decoders but requires 99 and 31% more LUTs and FFs with extra RAM usage than the proposed decoder. Moreover, the hardware utilization efficiency (HUE) is also estimated for all the designs based on the work [36,37]. HUE is the ratio of the throughput to the LUT, FF, and BRAM utilization. ...
Polar codes are the popular error-correcting codes and increased their attention after being adopted for the control channel in fifth-generation new radio (5G NR) standards. An efficient hardware architecture for polar code is often required with minimal encoding and decoding complexity. This work proposes a Multi-folded pipelined architecture and analyzes the performance in terms of latency, hardware utilization, and throughput. The designed architecture has two folded architectures interconnected in parallel to output 4-bits simultaneously. Folding transformations are used to reduce the number of idle processing elements (PEs) in every stage leading to the effective utilization of PE. Precomputation is effectively utilized in the PE to reduce the critical path delay, which improves the maximum operating frequency. A Loop-based shifting register (LSR) is employed to reduce the number of registers used. The analytical model for latency and utilization rate has been derived from the scheduling of the proposed architecture. The proposed design shows 63–71% higher hardware utilization than conventional semi-parallel design for code length \(N=512\) suitable for the physical downlink control channel (PDCCH) in 5G NR. The architecture is also implemented in Virtex-6, ZYNQ-Ultrascale+ MPSoC device for maximum supported code length of 5G NR, i.e., up to \( 2^{10} \), compared with the existing decoders. The proposed design also has the benefit of lesser look-up-table (LUT) consumption and zero random-access-memory (RAM) usage with some additional registers, making it suitable for resource-constraint applications.
... LDPC decoders offer a low-complexity implementation compared to other forward error-correcting codes, according to [15,49,50]. ...
... In contrast to the MAP algorithm used by the SISO decoder from the classic turbo equalization scheme, which requires a large memory as well as many multiplication and exponentiation operations [51], the min-sum algorithm used by the LDPC decoder of our proposed system simplifies the computational complexity by using simple arithmetic operations according to [50]. ...
In this article we present an iterative system of equalization and decoding to manage the intersymbol interference over an additive white Gaussian noise (AWGN) channel. Following the classic turbo equalization scheme, the proposed system consists of low-density parity-check (LDPC) coding at the transmitter side; we applied a Log maximum a posteriori probability (Log-MAP) equalizer and min-sum LDPC decoding at the receiver side. The equalizer and decoder, linked through interleaving and deinterleaving, iteratively update each other’s information. We performed the performance analysis of the proposed system, bit error rate (BER) vs. signal-to-noise ratio (SNR), considering three different impulse responses of the channel (h). Our experimental results indicated that increasing the number of iterations performed by the LDPC decoder from 10 to 20 during the iterative process of equalization and decoding leads to better outcomes. The proposed system was compared with turbo equalization and separate equalization, performed before the decoding process with minimum mean-square error (MMSE) and LDPC decoding, in terms of BER vs. SNR, considering the three different h. Based on the analyzed results, it can be concluded that the equalization performance depends on both the impulse responses of the channel and the chosen decoding and equalization method; therefore, the equalization method does not always offer good results for any h.
... In another investigation, the throughput and hardware usage efficiency for regular and irregular LDPC codes were augmented using the Minimum-Sum (MS) algorithm on the base matrix (BG1) of the 5G standards. It was noted that while more iterations improved error correction, they concomitantly increased the decoding time [28]. ...
... HE is the hardware efficiency calculated as the ratio of throughput to the number of LUTs, FFs, and RAM usage, as reported in [34,35] compared with the SCL decoder which had superior error-correcting performance in terms of HE. The SCL decoder has proven error-correcting performance at the cost of extra hardware based on the list size. ...
A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder archi-tectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10 À4 at 2.7 E b /N o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication. K E Y W O R D S 5G new radio, belief propagation, field-programmable gate array, low-density parity-check code, pipeline, polar code
The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10−6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving.
