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Quantum dot cellular automata i.e. QCA is risen as a result of tremendous examination made by scientists to discover a productive nanoscale substitution of CMOS technology. The nanoscale execution of CMOS additionally experiences high power dispersal. In this present article a thorough study has been made to discuss the benefits of square sturcture...
Citations
... Repulsion of electrons and movement between the dots inside cells are utilized for information processing. Different combinations of dots and electrons are proposed for realization [7][8][9]. But the four dots, and two electron structure is the extensively used structure in the literature. ...
Quantum-dot Cellular Automata (QCA) is a nontransistor-based nanotechnology circuit design paradigm. The circuits are implemented by using cells having quantum dots and electrons. There are several cell configurations with varying combinations of electrons and quantum dots. But the widely used cells have the four-dot two-electron structure. Circuits are realized and validated by using QCADesigner. However, the layouts are developed manually by using this tool. Layouts are not entirely automated in QCA. Hence, in this work, the existing QCA tools and the different techniques proposed in the literature to improve the QCA layout generation are analyzed and a complete framework for QCA layout generation is proposed. It also explores the gap that needs to be filled to achieve a reliable CAD tool for QCA layout generation. In addition to that, to design circuits using rotated cells, design rules and cost functions are proposed. Novel circuits of multiplexer and D-flip-flop are also proposed using rotated cells. The proposed designs have better output polarization compared to other designs. Verification is done in QCADesigner.
Quantum-dot Cellular Automata (QCA) nanotechnology is an interesting circuit design technology which is based on columbic repulsion and Majority logic. Reliability is a key issue in QCA circuits. In this work, an adder is proposed with better fault tolerance and reduced complexity by combining 3-input majority logic and 5-input majority logic gates. The proposed design is realized by using clock zone approach. Hence, the proposed design deploys only normal cells for its realization. This makes the proposed design less vulnerable to fabrication faults. This is validated by performing extensive fabrication defect analysis. A novel expression to compute the circuit complexity is also proposed. The proposed multipliers consume almost 55% lesser energy compared to the existing designs. The proposed adder is used to realize a reliable array and serial multiplier. The proposed adder can be used in any circuits at the basic elements.
