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(a) An example showing Huffman code and tree-based code. (b) The Huffman tree. (c) The simpli fi ed Huffman tree.
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A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can b...
Contexts in source publication
Context 1
... an example, assume that S includes seven unique symbols as depicted in Fig. 5(a). According to the prob- abilities of these symbols, the Huffman tree can be con- structed as shown in Fig. 5(b). If we partition S into Consequently, the codewords of the tree-based code can be obtained, as depicted in Fig. ...
Context 2
... an example, assume that S includes seven unique symbols as depicted in Fig. 5(a). According to the prob- abilities of these symbols, the Huffman tree can be con- structed as shown in Fig. 5(b). If we partition S into Consequently, the codewords of the tree-based code can be obtained, as depicted in Fig. ...
Context 3
... an example, assume that S includes seven unique symbols as depicted in Fig. 5(a). According to the prob- abilities of these symbols, the Huffman tree can be con- structed as shown in Fig. 5(b). If we partition S into Consequently, the codewords of the tree-based code can be obtained, as depicted in Fig. ...
Citations
... The algorithmic approach is fast and provides better fault coverage [9]. The stuck-at fault, transition fault, address decoder faults, neighbourhood pattern sensitive faults (NPSF), and coupling faults computes by memory built-in self-test (MBIST) approach [9,12,16,17,18,19,20]. The research approaches [21,22,23] are not able to detect all fault types in semiconductor memories. ...
System on Chip (SoC) architecture mainly consists of the memories in a larger area. Due to the availability of memories in a larger-size, it is difficult to test these memories for faults. Therefore, a smooth test solution to test these memories against fault and repair the faulty cells has introduced. In this research, we proposed a Memory Test Controller (MTC) to test the memories and Built-in Self-repair (BISR) mechanism to repair the faulty cells for any recent SoC based devices. The MTC not only identifies the fault, but it finds the type of fault available, and BISR block repairs the detected faulty cells. The paper provides empirical insights about how change is brought in features of the SoC based device after integrating both the proposed controller block. It is noticed that from the obtained results, the proposed methods are stands better in terms of the area overhead, power and timing when compared with the existing approaches.
... Some of interaction signals between the BIST and BIRA are shown in the figure, which are faulty address (FA), syndrome (SYN), and repair (REP). Once the BIST detects a fault, the corresponding FA and Hamming syndrome are sent to the BIRA through the FA and SYN, where Hamming syndrome is defined as the modulo-2 sum of the fault-free data output vector and the output vector from the RAM under test [32]. The signal REP is used to indicate the RA result of the BIRA is repairable or unrepairable. ...
A built-in self-repair (BISR) scheme for random access memories (RAMs) with 2-D redundancy has a built-in redundancy analyzer (BIRA) for allocating the redundancy. The BIRA typically has a cache-like element called local bitmap for storing the fault information temporary. In this paper, a high-repair-efficiency BISR (HRE-BISR) scheme for RAMs is proposed. The HRE-BISR reuses the local bitmap to serve as spare bits such that it can repair more faults. In addition, a row/column/bit redundancy analysis (RCB-RA) algorithm for a RAM with spare rows, spare columns, and spare bits is presented. Simulation results show that the proposed HRE-BISR scheme can provide higher repair rate (RR) than a typical BISR scheme without reusing the local bitmap as spare bits. Only about 0.44% additional hardware overhead is needed to modify the local bitmap as spare bits. In addition, the HRE-BISR scheme using -bit local bitmap for RA only incurs about 0.08-ns delay penalty for a -bit RAM with one spare row and one spare column. However, the HRE-BIRA scheme with RCB-RA algorithm can provide 0.48%–11.95% increment of RR for different fault distributions.
... Testing embedded-memory cores has been a big challenge for SoC testing due to the difficulty of test isolation and test accessibility [8]. By reducing the tester requirement and enabling the parallel testing of different memory cores, memory built-in-self-test (BIST) circuit is the best solution to the embedded memory testing in common consensus today [9][10][11]. Several BIST schemes are proposed for the embedded DRAM testing [12][13][14][15]. ...
The embedded-DRAM testing mixes up the techniques used for DRAM testing and SRAM testing since an embedded-DRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. The experimental results are collected based on 1-lot wafers with an 16 Mb embedded DRAM core.
... Reliability enhancement techniques for memory cores during life time thus is imperative. Conventional memory BIST (off-line BIST) is a promising approach for embedded memory testing and diagnosis [1,7,10,16], which is helpful for improving the yield of memories during manufacturing phase. However, off-line BISTs cannot be used for testing memories during life time. ...
Memory cores are usually the densest portion with the smallest feature
size in system-on-chip (SOC) designs. The reliability of memory cores
thus has heavy impact on the reliability of SOCs. Transparent test is
one of useful technique for improving the reliability of memories during
life time. This paper presents a systematic algorithm used for
transforming a bit-oriented march test into a transparent word-oriented
march test. The transformed transparent march test has shorter test
complexity compared with that proposed in the previous works [Theory of
transparent BIST for RAMs, A transparent online memory test for
simultaneous detection of functional faults and soft errors in
memories]. For example, if a memory with 32-bit words is tested with
March C-, time complexity of the transparent word-oriented test
transformed by the proposed scheme is only about 56% or 19% time
complexity of the transparent word-oriented test converted by the scheme
reported in [Theory of transparent BIST for RAMs] or [A transparent
online memory test for simultaneous detection of functional faults and
soft errors in memories], respectively.
... The address difference between the word under test (WUT) and the last faulty word, d, is represented using the address levels as shown in Table 1. The Compressed Syndrome is obtained from compressing the Word Syndrome by Huffman Code [7] ...
Embedded memory diagnostics is normally done by the built-in self-diagnosis (BISD) hardware, which collects and sends the diagnostic data to the external tester. The cost of the diagnosis process highly depends on the data volume sent between the chip under test and the tester, since the transmission time and the tester capture memory are major cost factors. We propose a memory BISD design using differential addressing, as well as a method for evaluating and choosing a proper differential address level. Based on our previous work on pattern identification BISD and syndrome compression design, the proposed differential address compression scheme further reduces the diagnostic data volume. Experimental results show that the BISD design is cost-effective.
... Reliability enhancement techniques for memory cores during life time thus is imperative . Conventional memory BIST (off-line BIST) is a promising approach for embedded memory testing and di- agnosis [1, 7, 10, 16], which is helpful for improving the yield of memories during manufacturing phase. However, off-line BISTs cannot be used for testing memories during life time. ...
Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has a heavy impact on the reliability of SOCs. The transparent test is a useful technique for improving the reliability of memories during their life time. The paper presents a systematic algorithm used for transforming a bit-oriented march test into a transparent word-oriented march test. The transformed transparent march test has shorter test complexity compared with those proposed previously (Nicolaidis, M., IEEE Trans. Computers, vol.45, no.10, p.1141-56, 1996; Thaller, K. and Steininger, A., IEEE Trans. Reliability, vol.52, no.4, p.413-22, 2003). For example, if a memory with 32-bit words is tested with March C-, the time complexity of the transparent word-oriented test transformed by the proposed scheme is only about 56% and 19% of the time complexity of the transparent word-oriented test converted by the schemes reported by Nicolaidis and by Thaller and Steininger, respectively.
... Test data compression methods can reduce the volume of test data applied to the core under test (CUT) or the volume of test responses sent to the ATE. Test response compression is carried out using signature analyzers [18], however, if diagnosis is necessary special schemes may be required [19,20]. In this paper, we will focus on the former due to the large volumes of test data required to test logic cores, assuming signature analyzers to compress the test output responses. ...
This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environment (TDCE) parameters: compression ratio, area overhead, and test application time, and explains the impact of the factors which influence these three parameters. The proposed method is based on a new variable-length input Huffman coding scheme, which proves to be the key element that determines all the factors that influence the TDCE parameters. Extensive experimental comparisons show that, when compared with three previous approaches, which reduce some test data compression environment's parameters at the expense of the others, the proposed method is capable of improving on all the three TDCE parameters simultaneously.
As fault occurrence probability has increased with corresponding increases in memory density and capacity, memory test and repair have been widely used. However, the total cost for these has increased dramatically due to the increased cost of automatic test equipment (ATE) and the time required for redundancy analysis (RA). The increase in ATE cost has been caused by the increased size of fail address memory, where memory fault information is stored during memory test. The RA time has also increased because the difficulty encountered during fault analysis has increased in proportion to the increase in the number of memory faults. To address these problems, an RA-aware fail data collection architecture is proposed. This includes a new fail address memory structure that can significantly reduce the fail address memory size. Moreover, the architecture can integrate memory fault information using simple calculations without any data losses. In addition, unnecessary memory fault information can be eliminated easily with efficient data encoding to reduce the data size. Furthermore, since some information required for fault analysis in memory repair can be collected during memory test, the RA time needed to find memory repair solutions is also reduced without any degradation in the repair rate. Consequently, the total cost for memory test and repair can be considerably reduced by reducing the cost of ATE and the RA time. Experimental results reveal that the fail address memory size and RA time can be reduced by an average of 63% and 41%, respectively, with the proposed architecture.
Memory test and repair has been generally applied to improve memory yield. However, due to the high cost of automatic test equipment (ATE) equipment, which has been employed for memory test and repair, there is a significant focus on reducing the ATE expense. One of the major problems, which contribute to the increase in ATE cost, is fail address memory. The size of fail address memory, where memory fault information is stored during the memory test, has continuously grown in line with the memory capacity increase. To address the problem, a new fail address memory architecture for cost-effective ATE is proposed in this paper. In the proposed architecture, memory fault information is compressed and unrequired memory fault information is eliminated. In addition, a new structure of fail address memory is used to efficiently store memory fault information. Accordingly, the size of fail address memory is highly reduced in the proposed architecture. Furthermore, since some information, which can be used during the memory repair, can be collected during the memory test, the redundancy analysis time required to find memory repair solutions is also reduced in the proposed architecture. The advantages were verified experimentally.
This Major portion of the SoC's are covered by memories. Dense design creates a wide variety of faults leading to the failures in the memory functions. Built-in self-test (BIST) mechanism is a promising method to test and diagnose embedded memories like RAMs. The advantages include reduced test cycle duration and fewer complexes. March tests are widely used in production test thanks to their low time complexity and high fault coverage. They were capable of locating and identifying the fault types. Diagnostic data exportation by the BIST is time — consuming since it is exported bit-by-bit. To overcome this, a BIST with March-element-based (MEB) Compression scheme is proposed. MEB Compression scheme can efficiently compress the diagnostic data of a RAM tested by a March test. To optimize the performance of the BIST controller, another design is also proposed here. Detection of different faults in a RAM memory using a single counter based BIST design is advantageous. As a result a fusion of March algorithms like MATS, March C and March X are used for the detection of Stuck-at fault, Coupling fault and Transition fault respectively. Advantages of counter-based BIST architecture includes reduced area overhead and complexity. Compression of the test data is carried out using a decoder module. The implementations are carried out by using Verilog Hardware description language and Xilinx ISE 13.2 design suite. Experimental results shows that the proposed methods reduces the fault detection time, redundant diagnostic data, tester storage requirement, area overhead and complexity in the design.
