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This paper describes the architecture, design & implementation of 2 bit ternary ALU (T-ALU) slice. The proposed ALU is designed for two-bit operation & can be used for n bit operations by cascading n/2 ALU slices. This ALU is implemented using C-MOS ternary logic gates (T-Gates) for ternary arithmetic & logic circuits. Ternary gates are implemented...
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Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, au...
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... Its columns correspond to 0, 1, and 2, respectively. 2. Transform Z (+ 1) shifts the qutrit states by 1. 3. Transform Z (+ 2) shifts the qutrit states by 2. 4. Transform Z (12) swaps (permutes) the qutrit states |1> and |2>. 5. Transform Z (01) swaps the qutrit states |0> and |1>. ...
... The truth table of those operations is shown in Table 0. 2. Assume every operation is in the quantum system. ...
... Based on the operating principle, a General Ternary Inverter (GTI) can be of three types: Negative, Positive, and Standard. A GTI is represented by Equation (1), Equation (2) and Equation (3), where x is the input and y0, y1 and y2 are the outputs that represent a Negative Ternary Inverter (NTI), a Positive Ternary Inverter (PTI) and a Standard Ternary Inverter (STI), respectively [28]. The truth table that represents the functions y0, y1, and y2 which is shown in Table 2. Our work is based on Standard Ternary Inverter (STI). ...
DNA (Deoxyribose Nucleic Acid) computing has the features of parallel processing and large storage capability that make it special from other conventional computing systems. It is a type of biomolecular programming where different types of reactions are used to perform basic operations and the processing information is stored in nucleic acids and proteins. The traditional ROM (Read Only Memory) is a slower memory. Thus, the multi-valued DNA computing enables the creation of new types of computers which is capable of operating multiple sequences as input states by increasing storage capacity. In this paper , a multi-valued DNA-based ROM architecture is designed using proposed algorithms of multi-valued DNA-based operations.
... Now the product which is in the DBNS domain is converted again in RNS for performing RNS based add operation [10], [27]. Ternary domain-based MNS MAC unit is enacted using double base ternary number system (DBTNS) multiplier and ternary residue number system (TRNS) adder [8], [9], [29]. The architecture of the ternary domain-based mixed number system based MAC unit is shown in Fig. 2 ...
... The CNTFET circuit implementation also includes dual-logic gates [18], three-input logic gates, MVL [19], and binary memory cells [20]. The use of carbon nanotubes for MVL has received much attention since the threshold voltage of CNTFETs may be maintained with selected CNTFET chiral vectors [21][22][23]. In MVL, we have three different stages in which more specific parameters of a circuit can be specified [24]. ...
The design of a three-input logic circuit using carbon nanotube field effect transistors (CNTFETs) is presented. Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices, which is why this design is so popular, and it also reduces chip area, both of which are examples of circuit overheads. The proposed module we have investigated is a triple-logic-based one, based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values, as well as comparisons of the design working with various load capacitances. Comparing the proposed design with the existing design, the delay times was reduced from 66.32 to 16.41 ps, i.e., a 75.26% reduction. However, the power dissipation was not optimized, and increased by 1.44% compared to the existing adder. The number of transistors was also reduced, and the product of power and delay (P∗D) achieved a value of 0.0498053 fJ. An improvement at 1 V was also achieved. A load capacitance (fF) was measured at different values, and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps, with a range of 61.06 ps. The power dissipations ranged from a minimum of 3.38 μW to a maximum of 6.49 μW. Based on these results, the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.
... In practice, using MVL increases the speed and reduces the area and power consumption of the chip. For example, if used correctly in the design of a multi-valued multiplier, MVL can make up to 50% reduction in chip area and power consumption compared to binary alternatives [23]. Another advantage of MVL is the reduction in memory size because the bigger radix needs fewer memory cells to store the data [23]. ...
... For example, if used correctly in the design of a multi-valued multiplier, MVL can make up to 50% reduction in chip area and power consumption compared to binary alternatives [23]. Another advantage of MVL is the reduction in memory size because the bigger radix needs fewer memory cells to store the data [23]. ...
Full adder is one of the essential circuits among
the various processing elements used in VLSI and other
technologies circuits, because they are mainly employed in
other arithmetic circuits, such as multi-digit adders,
subtractors, and multipliers. This paper proposes two
efficient ternary full adders based on Carbon Nanotube
Field-Effect Transistor (CNFET) technology. Using the
adjustable nanotube diameter in CNFETs, these adders
utilize arbitrary threshold voltages so that arithmetic
operations can be performed with a radix of 3. For
performance analysis, the proposed adder circuits are
simulated in HSPICE with 32nm CNFET technology. In
these simulations, different inputs are applied at different
frequencies with different load capacitances placed at the
output. Simulation results have shown that the proposed
adders not only improve the speed, power consumption, and
Power Delay Product (PDP) of the existing state-of-the-art
designs but also improve the design complexity by reducing
the number of transistors contained within the circuit.
... latches are level-sensitive elements that hold data when the clock is low, while registers are edge-sensitive that hold data when the clock rises. The D flip-flop is by far one of the most common clocked flip flops [12]. A simple circuit was first proposed by William Eccles and F. W. Jordan [13]. ...
... The performance analysis of the proposed designs against the CMOSbased designs, reported in Refs. [11,12] and against CNTFET based design, reported in Ref. [19], is depicted in Table 5. This comparative study shows that the dynamic DFF provides the best performance with respect to power, delay, and area. ...
Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures.
... Here, resistors are inserted in between the transistors to get the required intermediate voltage level [29]. Fig. 3 shows the DC transfer characteristics of the circuit of Fig. 2. The same circuit can be constructed without using the resistors and controlling the threshold voltage [34]. All these techniques and circuits can be extended to implement ternary NAND, NOR, ALU, adder, multiplier, etc. complex circuits [30], [31], [34], and [35]. ...
... Fig. 3 shows the DC transfer characteristics of the circuit of Fig. 2. The same circuit can be constructed without using the resistors and controlling the threshold voltage [34]. All these techniques and circuits can be extended to implement ternary NAND, NOR, ALU, adder, multiplier, etc. complex circuits [30], [31], [34], and [35]. ...
Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review paper, different technologies for Multiple-Valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic.
... Based on the operating principle, a General Ternary Inverter (GTI) can be of three types: Negative, Positive, and Standard. A GTI is represented by (1), (2) and (3), where x is the input and y0, y1 and y2 are the outputs that represent a Negative Ternary Inverter (NTI), a Positive Ternary Inverter (PTI) and a Standard Ternary Inverter (STI), respectively [21]. The truth table that represents the functions, y0, y1, and y2, is shown in Table II. ...
... From the Table, it can be observed that, in terms of delay, total power, and PDP, our proposed logic gates hold a lot of promise in the field of ternary devices. Fig. 19 shows the delay comparison of three different types of ternary half-adder circuits presented in [6], [21], and [31] with the proposed GNRFET based half-adder. Here, T1 = 0-1 rise time delay of "Sum" with respect to "B" T2 = 1-2 rise time delay of "Sum" with respect to "B" T3 = 0-1 rise time delay of "Carry" with respect to "B" T4 = 0-1 rise time delay of "Sum" with respect to "A" It is observed that the delay in the proposed GNRFET based half-adder design is much lower than the other three designs. ...
Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET e.g. the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL device. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and small circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the proposed GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website.
... There have been several ternary ALU designs reported in the literature. A ternary ALU based on CMOS implementation is proposed in [5] which uses the decoders, ternary gates and ternary buffers to implement the ALU modules such as an adder, subtractor and multiplier. However, ALU design [5] employs depletion type MOSFETs and large off-chip resistors in the circuit leads to large power dissipation and area overhead. ...
... A ternary ALU based on CMOS implementation is proposed in [5] which uses the decoders, ternary gates and ternary buffers to implement the ALU modules such as an adder, subtractor and multiplier. However, ALU design [5] employs depletion type MOSFETs and large off-chip resistors in the circuit leads to large power dissipation and area overhead. The ternary ALU (T-ALU) design based on CNFET is presented in [14] which is the improved version of [5]. ...
... However, ALU design [5] employs depletion type MOSFETs and large off-chip resistors in the circuit leads to large power dissipation and area overhead. The ternary ALU (T-ALU) design based on CNFET is presented in [14] which is the improved version of [5]. The adder and subtractor modules are embedded into one block and multiplexed the outputs using ALU select signals. ...
This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits.
... A ternary multiplier cell has two trits of input and two trits of output including a product and a carry trit (ternary digit). Equation (3) shows the equation of a ternary multiplier [26]. ...
In this paper, a new method for multiplying two n-trit numbers using CNFET and ternary logic is introduced. The carry resulted from the ternary multiplier never takes the value of two and is always zero or one. In this paper, this feature of the carry is used to construct two novel capacitive and transistor structures for reducing the partial product tree. These structures simultaneously improve the power consumption and latency, and the higher is the number of the trits of the two multiplied numbers, the increase in this improvement will be more. In this paper, on average, the proposed capacitive structure improves power consumption, latency and PDP as much as 26.72%, 9.74% and 33.8% respectively compared to the original structure. This improvement for the proposed transistor structure will be changed to 26.67%, 8.77% and 33.04% respectively. The reason for the lower improvement in the transistor structure is the overhead in this structure, which will be examined.
