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(a) A floating gate NAND Flash memory cell which stores charge in the floating gate (or charge trap layer). Metal WL of the array is connected to the control gate. Electron tunneling takes place through tunnel oxide from transistor channel to FG. Blocking oxide prevents back tunneling of stored charge to control gate. (b) Typical current-voltage characteristics of the memory cell. (c) The hierarchical storage in NAND Flash array consisting of kilo-bytes of memory cells connected through a single word line (called a page of information). A group of word-line forms a block of memory. The select gate transistors can be standard MOSFET or floating gate transistors, depending on manufacturers or technology node.
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... Memory Cell: The device structure of a single Flash memory cell is shown in Fig. 1 As shown in Fig. 1(b), V T of the transistor depends on the current-voltage characteristics, where a fixed sense current (I sense ) is usually used to determine the exact V T . During a read operation, a fixed "read reference voltage" (V ref ), which is lower than the programmed voltage, is applied to the control gate. Based on the V T ...
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... Memory Cell: The device structure of a single Flash memory cell is shown in Fig. 1 As shown in Fig. 1(b), V T of the transistor depends on the current-voltage characteristics, where a fixed sense current (I sense ) is usually used to determine the exact V T . During a read operation, a fixed "read reference voltage" (V ref ), which is lower than the programmed voltage, is applied to the control gate. Based on the V T of the transistor, ...
Context 3
... cycle 280, the value of erase time is again showing a shift from 6800us to 7000us. This pattern is clearly stating that, as the number of program-erase cycle will increase, the value of erase time will increase accordingly. Physically, PE cycle creates defects in the tunnel oxide and in the Si-oxide interface of the Flash memory cells as shown in Fig. 1 (a). The defects thus reduce the cell current of the Flash cell which makes the erase operation difficult and hence erase time increases. Another interesting point from 4 (a) is that the erase time increases in steps. The reason for such behavior is the fact that the erase operation in the NAND flash takes place in multiple pulses or ...
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Citations
... Electrical testing can also be employed to detect counterfeit [13] but are not equally applicable to all types of chips, may require expensive measurement setups, and are time-consuming. Recycled flash memory can be detected using a framework that uses partial programming technique [17] or by observing the erase time [22]. Recycled SRAM can be detected by detecting aging sensitive SRAM cells [16]. ...
Counterfeit electronics have widespread im-pacts on the many aspects of modern civilization thatdepend on integrated circuits (ICs) or chips. Among allof the counterfeit chips types, recycled and remarkedare the most prevalent. These are the chips that aretaken from discarded, obsolete electronics board andthen sold as new. As a result, they are aged and de-teriorated with short remaining lifespan and prone tofailure. Silicon odometers have been proposed to detectrecycled digital ICs, but few are applicable to analogand mixed signal (AMS) chips. Recently, an odometerthat can be integrated into a common AMS IP block,the low dropout regulator (LDO), was proposed. However, it has high area overhead, requires external mea-surements for classification, and has a security vulnera-bility. In this article, self-contained LDO odometers areproposed that overcomes these issues while still beingable to detect aging in AMS and digital chips. A calibra-tion feature is also introduced to compensate for processvariation. The area overhead of the analog and digitalversions are 8μm2 and 3.3μm2, respectively, which arean order of magnitude smaller than the prior state-of-the-art. A detection accuracy of 98.2% and 99.5% havebeen achieved for each which are comparable to existing odometers.
... This technique is useful in cases of recycled counterfeits. Similarly, Kumari et al. [30] provide a low-cost detection method for recycled memory chips which are incorporated in many electronic systems. The detection method depends on studying the chips' timing characteristics, which are sensitive to high usage, program, and read time [30,31]. ...
... Similarly, Kumari et al. [30] provide a low-cost detection method for recycled memory chips which are incorporated in many electronic systems. The detection method depends on studying the chips' timing characteristics, which are sensitive to high usage, program, and read time [30,31]. ...
One of the major threats to the information and communications technology (ICT) supply chain is the introduction of counterfeit parts and components. Global efforts have been intensified to defend against counterfeiters and counterfeit products due to their detrimental impact on the economy, safety, and security. Among the extensive literature of papers, reviews, books, and articles, this review attempts to include a detailed selection of most significant research work done in the intersection of ICT, supply chains, and counterfeits to provide a reference source for researchers. Citation network and global citation scores have been used to extract and analyze papers and discuss them in different types of clusters (electronic, medical, food, and anti-counterfeiting technologies and approaches). Our review approaches the clustered papers by focusing on (1) their contribution in documenting and modeling the intrusion of counterfeit electronic parts in the ICT supply chain, (2) the proposed counterfeits’ detection and avoidance techniques in the ICT supply chain, and (3) the contribution of ICT in thwarting counterfeits in medical, pharmaceutical, and food supply chains. This review provides a better understanding of the global efforts to address counterfeits in the ICT supply chain, as well as the role of ICT in thwarting counterfeits in other supply chains, which can guide future research to minimize the impact of counterfeits on supply chains.
... Counterfeiting of Integrated Circuits (ICs) is a significant concern for the semiconductor supply chain [1]. Reliability and security issues of counterfeited or degraded Non-Volatile Memory (NVM) chips have the potential to threaten various sectors such as automotive, defense/security, medical devices, consumer electronics, etc. [1], [2]. Variation in nanoscale properties of different NVM technologies occurs due to variation in underlying nanostructures and nanomaterials. ...
... Variation in nanoscale properties of different NVM technologies occurs due to variation in underlying nanostructures and nanomaterials. Various invasive and non-invasive techniques exist in literature which can be employed on Commercial-Off-The-Shelf (COTS) chips to detect IC origin [3] or recycled ICs [1], [2], [4], [5]. In addition, other security primitives like chip identity information, memory-based Physical Unclonable Functions (PUFs) [6], True Random Number Generator (TRNG) [7], etc. are implemented to track NVM chips. ...
... In addition, other security primitives like chip identity information, memory-based Physical Unclonable Functions (PUFs) [6], True Random Number Generator (TRNG) [7], etc. are implemented to track NVM chips. However, most of these techniques are proposed for NAND Flash memory [2] or DRAM [3] chips. Moreover, detailed chip characterization and maintenance of large database for ascertaining COTS NVM chip authenticity is cumbersome. ...
This study presents a methodology for anticounterfeiting of Non-Volatile Memory (NVM) chips. In particular, we experimentally demonstrate a generalized methodology for detecting (i) Integrated Circuit (IC) origin, (ii) recycled or used NVM chips, and (iii) identification of used locations (addresses) in the chip. Our proposed methodology inspects latency and variability signatures of Commercial-Off-The-Shelf (COTS) NVM chips. The proposed technique requires low-cycle (~100) pre-conditioning and utilizes Machine Learning (ML) algorithms. We observe different trends in evolution of latency (sector erase or page write) with cycling on different NVM technologies from different vendors. ML assisted approach is utilized for detecting IC manufacturers with 95.1 % accuracy obtained on prepared test dataset consisting of 3 different NVM technologies including 6 different manufacturers (9 types of chips).
... It is crucial to use trusted memory chips in order to ensure security in critical applications. Although there are a few works on detecting different recycled memory chips such as SRAM [8] or flash memory [9], no such experiment on DRAM aging is available. Tehranipoor et al. [10] discuss the aging effects that degrade DRAM chips and explore its impact reliability of DRAM-based PUF but do not address its use in recycled chip detection. ...
The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips’ statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error.
... NAND flash memory exhibits limited endurance, which is typically specified by the maximum number of program-erase operations (or PE cycles) allowed on a memory block. The number of PE cycles may impact the nominal page program time, t prog , and stressed pages with a high number of PE cycles may take more time to program [29][30][31]. Hence, an implementation of EXPRESS needs to consider the number of PE cycles. Figure 12a shows the cumulative distribution of the nominal page program time for SLC pages in a fresh flash memory block, and in a memory block that has been exposed to 10,000 PE cycles. ...
The density and cost-effectiveness of flash memory chips continue to increase, driven by: (a) The continuous physical scaling of memory cells in a single layer; (b) The vertical stacking of multiple layers; and (c) Logical scaling through storing multiple bits of information in a single memory cell. The physical properties of flash memories impose disproportionate latency and energy expenditures to ensure the high integrity of the data during flash memory writes. This paper experimentally explores this disproportionality on state-of-the-art commercial 3D NAND flash memories and introduces EXPRESS—a technique for increasing the energy efficiency of flash memory writes by exploiting the premature termination of the flash write operations. An experimental evaluation shows that EXPRESS reduces energy expenditures by 20–50%, relative to the traditional flash writes, at the cost of a minimal loss in the data integrity (<1%). In addition, we evaluate the effects of the page-to-page variability, program–erase cycling, and data retention on the implementation of EXPRESS, and we propose enhancements to counter these effects.
... Another paper from Kumari et al. [62] uses less invasive techniques to extract latency values from aged flash chips in order to detect counterfeits. Instead of a partial programming burst, the latency of different operations such as program and erase is used. ...
... Logistic regression (LR), support vector machines (SVM), and artificial neural networks (ANN) were used. This expanded the work from Kumari et al. [62], enhancing their detection scheme by achieving a counterfeit detection accuracy greater than 97.5% , only requiring 0.05% to 0.96% of the total P/E cycling endurance used. Furthermore, the author used three extra features besides the erase, programming, and bit error metrics used in the previous work to increase the accuracy. ...
Over the last two decades, hardware security has gained increasing attention in academia and industry. Flash memory has been given a spotlight in recent years, with the question of whether or not it can prove useful in a security role. Because of inherent process variation in the characteristics of flash memory modules, they can provide a unique fingerprint for a device and have thus been proposed as locations for hardware security primitives. These primitives include physical unclonable functions (PUFs), true random number generators (TRNGs), and integrated circuit (IC) counterfeit detection. In this paper, we evaluate the efficacy of flash memory-based security primitives and categorize them based on the process variations they exploit, as well as other features. We also compare and evaluate flash-based security primitives in order to identify drawbacks and essential design considerations. Finally, we describe new directions, challenges of research, and possible security vulnerabilities for flash-based security primitives that we believe would benefit from further exploration.
... However, the proposed work cannot identify overproduction from the same foundry [5]. In the future, we will extend our technique for other volatile and non-volatile memory chips (e.g., flash memory, SRAM, etc. [62], [63]). Selecting a robust set of features to improve the accuracy might be another direction of our current research. ...
... High voltage is applied on the WL of the selected page during a program operation. It is very important to inhibit programming of the cells that should remain erased, which is typically controlled by the self-boosting technique [19]. However, unintentional (weak) programming still takes place on the erased cells, which may cause erased-to-programmed bit flips or PD errors. ...
This article demonstrates a novel technique for watermarking commercial off-the-shelf NAND flash memory chips. The technique uses repeated program-erase stressing to selectively control the physical properties of the flash cells and hence imprint watermark information into the flash media in an irreversible manner. It is accompanied by a watermark reading method that uses program disturb effects to extract the physical properties of flash memory cells containing watermark. The experimental evaluation, using several commercial flash memory chips, shows that the proposed technique offers robust watermarks that cannot be easily altered using fault injection attacks such as localized heating. We demonstrate a low bit error rate (<1%) in the retrieved watermark data and moderately high-speed watermark imprinting (
$\approx 1$
kb/s) and watermark retrieval (
$\approx 32$
kb/s). The proposed technique does not require any hardware modifications, making it a cost-effective anticounterfeit solution for a wide range of NAND-flash-based storage products.
... the brand value, but may also lead to catastrophic failure of mission-critical devices used in healthcare, finance, and national security [3]- [5]. The problem is getting more severe with the proliferation of low-cost, resource-constrained, Internet of Thing (IoT) platforms. ...
This article demonstrates a novel technique for generating aging-resistant, physical unclonable function (PUF) using commercial off-the-shelf NAND flash memory chips. The technique utilizes a novel "program-disturb" method using a single memory page to extract the inherent process variations unique to each chip. In addition, it employs an adaptively tunable PUF generation method to reduce the aging effects on PUF accuracy. The experimental evaluation utilizing several commercial flash memory chips shows that the proposed technique ensures accuracy, uniqueness, and randomness of PUFs generated from a single memory page for at least 1000 PUF-generating operations. Unlike prior flash PUF techniques, the proposed technique does not involve complex memory characterization or lengthy postprocessing steps, making it suitable for a wide range of resource constraint systems.
... However, the proposed work cannot identify overproduction from the same foundry [5]. In the future, we will extend our technique for other volatile and non-volatile memory chips (e.g., flash memory, SRAM, etc. [62], [63]). Selecting a robust set of features to improve the accuracy might be another direction of our current research. ...
Due to the globalization in the semiconductor supply chain, counterfeit dynamic random-access memory (DRAM) chips/modules have been spreading worldwide at an alarming rate. Deploying counterfeit DRAM modules into an electronic system can have severe consequences on security and reliability domains because of their sub-standard quality, poor performance, and shorter life span. Besides, studies suggest that a counterfeit DRAM can be more vulnerable to sophisticated attacks. However, detecting counterfeit DRAMs is very challenging because of their nature and ability to pass the initial testing. In this paper, we propose a technique to identify the DRAM origin (i.e., the origin of the manufacturer and the specification of individual DRAM) to detect and prevent counterfeit DRAM modules. A silicon evaluation shows that the proposed method reliably identifies off-the-shelf DRAM modules from three major manufacturers.
