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![(a) 16-bit ripple-carry-adder (RCA), (b) 16-bit almost correct adder (ACA) with maximal carry propagation length of 4 [6].](profile/Guillermo-Paya-Vaya/publication/271849890/figure/fig2/AS:667693082492940@1536201844649/a-16-bit-ripple-carry-adder-RCA-b-16-bit-almost-correct-adder-ACA-with-maximal.png)
(a) 16-bit ripple-carry-adder (RCA), (b) 16-bit almost correct adder (ACA) with maximal carry propagation length of 4 [6].
Source publication
Designing VLSI circuits for high temperature applications requires the use of specialized ASIC technologies suited for operation above 250° C. The technologies available today expose computation performance as well as the integration density far beyond state-of-the-art VLSI technologies. Especially at high temperatures, the switching speed of integ...
Contexts in source publication
Context 1
... all available adder architectures, the ripple-carry- adder (RCA) is the most straight-forward one. It is built up by connecting several full adder cells (1-bit basic adders for sum and carry) to a long chain (see Fig. 1a), which makes its critical path delay a linear function of its bit ...
Context 2
... possible implementation of an ACA with a maximum carry propagation length of 4 bit is shown in Fig. 1b. For 4-bit carry propagation, 6-bit PAs, e.g., using RCAs, are required. This adder architecture is referred to as ACA- RCA4 in the following. To mitigate the high degree of redundant computations within this implementation, a tree- like area saving method described in [6] was used. One further modification of this adder examined in ...
Context 3
... input values. The effect of decreasing the temperature to 175 • C is presented in Fig. 9. As it can be seen from the exemplary selected adders, the error distribution remains nearly the same but shifts to a higher K-factor. This effect can be explained by observing, that the path delays decrease almost linearly with the temperature. For that, in Fig. 11a and 11b the shape distribution of each path delay per adder remains 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 ...
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Citations
... Changes to the circuit timing require time-consuming re-synthesis of the design, which is narrowing the usability in variable timing cases, e.g., due to different voltage and temperature environments. For example, the chip design presented in Ref. [15] contains 16 different precise and approximate adder architectures for the purpose of exploring the stochastic behavior of arithmetic circuits within a wide range of ambient temperature and supply voltage conditions. Fabricated in a 1 μm high-temperature SOI CMOS technology, the operation range includes temperatures from 25 to 250C and supply voltages from 1.8 to 3.6 V. ...
ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic behavior, iterative timing analysis campaigns have to be carried out for a variety of circuit timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. Logic gates are instrumented with a quantization-based delay model and a critical path selection algorithm is used to reduce the FPGA resource overhead. For an exemplary design space exploration of stochastic CORDIC units, speed-up factors of up to 48 for 10 ps or 476 for 100 ps timing quantization are achieved while maintaining timing behavior deviations lower than 1.5% or 4% to timing simulations, respectively.
... The Stochastic ASIC [15] is a chip design created for analyzing the error characteristics of different adder architectures under out-of-specification conditions like high temperature, reduced supply voltage or frequency overscaling. For this purpose, precise (RCA, CLA, CSA) and approximate (ACA, ETA) 16 bit adder variants are implemented using a 1 μm high temperature SOI CMOS technology [13]. ...
ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. For an exemplary timing analysis campaign of an existing chip design, speed-up factors of up to 267 are achieved while maintaining timing behavior deviations lower than 1.05% to timing simulations.
... In a previous work [1], an application specific integrated circuit (ASIC) containing different approximate adder architec- tures was designed, simulated, and subsequently manufactured. In order to verify the simulation results and assess the real- world performance of the fabricated chip under different operating conditions, specialized testing equipment is necessary. ...
... In this section, the heating system is evaluated in a case study using the previously implemented, simulated, and fabricated "Stochastic ASIC" [1] as the DUT. Since the ASIC was fabricated in a 250 • C high temperature SOI process, its behavior at these temperatures is especially important. ...
This paper presents a newly developed integrated heating system, which can keep the IC under test at a constant temperature of up to 250 °C. The heating system can be used while the IC under test is mounted on its custom-designed interface board, which controls the two supply voltages and provides connectivity to an FPGA. Using a testing framework on the FPGA, the test stimuli and operating clock can be provided with at least 100 MHz. Thus, it is possible to fully vary all three parameters—frequency, voltage, and temperature—during continuous operation of the IC. A case study is performed with a previously fabricated ASIC to test the proposed system.
